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WM8232 Datasheet(PDF) 36 Page - Cirrus Logic

No. de pieza WM8232
Descripción Electrónicos  105MSPS 3-Channel AFE with Sensor
PDF  141 Pages
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Fabricante Electrónico  CIRRUS [Cirrus Logic]
Página de inicio  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8232 Datasheet(HTML) 36 Page - Cirrus Logic

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WM8232
36
Rev 4.6
Test Conditions
AVDD = LDOVDD = DBVDD = 3.3V, AGND = LDOGND = DBGND= 0V, TA = 25C, MCLK= 35MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
TGSYNC Setup time
(only for slave mode)
tSCKSY
tPER / 4
tPER / 2
3 * tPER / 4
ns
Pixel counter start timing
(only for slave mode)
tCOUNTD
2
clock
TGSYNC high period
(only for slave mode)
tSYH
1
clock
TGSYNC low period
(only for slave mode)
tSYL
1
clock
Data trigger timing delay
tTRIGD
LVDS 10-bit 5pair mode
22
clock
LVDS 10-bit 3pair mode
CMOS 10-bit output mode
20
clock
Other output mode
21
clock
TG pulse output timing delay
tPCKD
2
clock
Note:
1clock = tPER (MCLK cycle period)
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R160 (A0h)
7:4
OFFSET[3:0]
0000
offset count (only for slave mode)
2
POLSYNC
0
polarity of Sync signal
0 = positive edge, 1 = negative edge
1
TGMD
0
TG operation mode
0 = slave, 1 = master
0
TG_EN
0
TG enable
0 = disable, 1 = enable
R161 (A1h)
7:0
LLENGTH[7:0]
0000_0000
the number of pixels in 1line (only for master mode)
R162 (A2h)
6:0
LLENGTH[6:0]
000_0000
the number of pixels in 1line (only for master mode)
TG PULSE AND TRIGGER DATA
C_CK1
C_CK2
VSMP
TGCK
pixcnt
High@TP1
TP1
TP2
TP1
TP2
TP4
Low@TP2
High@TP4
TP4
TP6
TP5
Low@TP5
TP3
High@TP3
TP3
TP3
Low@TP3
High@TP4
TP4
TP6
Low@TP6
TP5
FLUGPIX
DataTrig
(FLUGPIX is selected )
Datatrig_out
(FLUGPIX is selected )
DataTrig
(P_CK1 is Selectd )
DataTrig
(P_CK1 is Selectd )
P_CK1
(Selected from P0-P7)
tTRIGD
tTRIGD
tTRIGD
TP3
P_CK2
(Selected from P0-P7)
P_CK3
(Selected from P0-P7)
Figure 24 TG Pulse Toggle Setting and Data Trigger Timing



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