COP8782CWM datasheet(8/28 Pages) NSC

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Functional Description (Continued)

TLDD11299 – 9

FIGURE 6 Interrupt Block Diagram

DETECTION OF ILLEGAL CONDITIONS

The device incorporates a hardware mechanism that allows

it to detect illegal conditions which may occur from coding

errors noise and ‘‘brown out’’ voltage drop situations Spe-

cifically it detects cases of executing out of undefined EP-

ROM area and unbalanced stack situations

Reading an undefined EPROM location returns 00 (hexade-

cimal) as its contents The opcode for a software interrupt is

also ‘‘00’’ Thus a program accessing undefined EPROM

will cause a software interrupt

Reading an undefined RAM location returns an FF (hexade-

cimal) The subroutine stack on the device grows down for

each subroutine call By initializing the stack pointer to the

top of RAM the first unbalanced return instruction will cause

the stack pointer to address undefined RAM As a result the

program will attempt to execute from FFFF (hexadecimal)

which is an undefined EPROM location and will trigger a

software interrupt

MICROWIREPLUS

MICROWIREPLUS is a serial synchronous bidirectional

communications interface The MICROWIREPLUS capabil-

ity enables the device to interface with any of National

Semiconductor’s MICROWIRE peripherals (ie AD con-

verters display drivers EEPROMS etc) and with other mi-

crocontrollers which support the MICROWIREPLUS inter-

face It consists of an 8-bit serial shift register (SIO) with

serial data input (SI) serial data output (SO) and serial shift

clock (SK)

Figure 7 shows the block diagram of the MICRO-

WIREPLUS interface

TLDD11299 – 10

FIGURE 7 MICROWIREPLUS Block Diagram

The shift clock can be selected from either an internal

source or an external source Operating the MICROWIRE

PLUS interface with the internal clock source is called the

Master mode of operation Operating the MICROWIRE

PLUS interface with an external shift clock is called the

Slave mode of operation

The CNTRL register is used to configure and control the

MICROWIREPLUS mode To use the MICROWIREPLUS

the MSEL bit in the CNTRL register is set to one The SK

clock rate is selected by the two bits SL0 and SL1 in the

CNTRL register Table IV details the different clock rates

that may be selected

TABLE IV

SL1

SL0

SK Cycle Time

2tc

4tc

8tc

where

tc is the instruction cycle time

MICROWIREPLUS OPERATION

Setting the BUSY bit in the PSW register causes the MI-

CROWIREPLUS arrangement to start shifting the data It

gets reset when eight data bits have been shifted The user

may reset the BUSY bit by software to allow less than 8 bits

to shift The device may enter the MICROWIREPLUS

mode either as a Master or as a Slave

Figure 8 shows how

two device microcontrollers and several peripherals may be

interconnected using the MICROWIREPLUS arrangement

Master MICROWIREPLUS Operation

In the MICROWIREPLUS Master mode of operation the

shift clock (SK) is generated internally by the device The

MICROWIREPLUS Master always initiates all data ex-

changes

(Figure 8) The MSEL bit in the CNTRL register

must be set to enable the SO and SK functions on the G

Port The SO and SK pins must also be selected as outputs

by setting appropriate bits in the Port G configuration regis-

ter Table V summarizes the bit settings required for Master

mode of operation

SLAVE MICROWIREPLUS OPERATION

In the MICROWIREPLUS Slave mode of operation the SK

clock is generated by an external source Setting the MSEL

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