COP8782CWM datasheet(10/28 Pages) NSC

10 / 28 page

Functional Description (Continued)

TLDD11299 – 12

FIGURE 9 TimerCounter Auto

Reload Mode Block Diagram

TLDD11299 – 13

FIGURE 10 Timer Capture Mode Block Diagram

TIMER PWM APPLICATION

Figure 11 shows how a minimal component DA converter

can be built out of the Timer-Register pair in the Auto-Re-

load mode The timer is placed in the ‘‘Timer with auto re-

load’’ mode and the TIO pin is selected as the timer output

At the outset the TIO pin is set high the timer T1 holds the

on time and the register R1 holds the signal off time Setting

TRUN bit starts the timer which counts down at the instruc-

tion cycle rate The underflow toggles the TIO output and

copies the off time into the timer which continues to run By

alternately loading in the on time and the off time at each

successive interrupt a PWM frequency can be easily gener-

ated

TLDD11299 – 14

FIGURE 11 Timer Application

Control Registers

CNTRL REGISTER (ADDRESS X’00EE)

The Timer and MICROWIREPLUS control register contains

the following bits

SL1

SL0 Select the MICROWIREPLUS clock divide-by

IEDG

External interrupt edge polarity select

(0 e rising edge 1 e falling edge)

MSEL

Enable MICROWIREPLUS functions SO and

TRUN

StartStop the TimerCounter (1 e run 0 e

stop)

TC3

Timer input edge polarity select (0 e rising

edge 1 e falling edge)

TC2

Selects the capture mode

TC1

Selects the timer mode

TC1

TC2

TC3

TRUN

MSEL

IEDG

Bit 7

Bit 0

PSW REGISTER (ADDRESS X’00EF)

The PSW register contains the following select bits

GIE

Global interrupt enable

ENI

External interrupt enable

BUSY MICROWIREPLUS busy shifting

IPND

External interrupt pending

ENTI

Timer interrupt enable

TPND Timer interrupt pending

Carry Flag

Half carry Flag

TPND

ENTI

IPND

BUSY

ENI

GIE

Bit 7

Bit 0

Addressing Modes

This is the ‘‘normal’’ mode of addressing for the device The

operand is the memory location addressed by the B register

or X register

DIRECT

The instruction contains an 8-bit address field that directly

points to the data memory location for the operand

IMMEDIATE

The instruction contains an 8-bit immediate field as the op-

erand

(AUTO INCREMENT AND DECREMENT)

This is a register indirect mode that automatically incre-

ments or decrements the B or X register after executing the

instruction

RELATIVE

This mode is used for the JP instruction the instruction field

is added to the program counter to get the new program

location JP has a range of b31 to a32 to allow a one byte

relative jump (JP a 1 is implemented by a NOP instruction)

There are no ‘‘pages’’ when using JP all 15 bits of PC are

used

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