ACE25AC100G

SPI NOR FLASH

VER 1.1

12

Chip Erase (CE) (60/C7H)

The Chip Erase (CE) command is for erasing the all data of the chip. A Write Enable (WREN) command

must previously have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE)

command is entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS#

must be driven Low for the entire duration of the sequence.

The Chip Erase command sequence: CS# goes low send Chip Erase command CS# goes high. The

command sequence is shown in Figure10. CS# must be driven high after the eighth bit of the command

code has been latched in, otherwise the Chip Erase command is not executed. As soon as CS# is driven

high, the self-timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in

progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write

In Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. Write

Enable Latch (WEL) bit is reset to 0 at the end of the Chip Erase cycle. The Chip Erase (CE) command is

ignored if one or more sectors are protected by (BP2, BP1, BP0) bits.

Read Manufacture ID/ Device ID (REMS) (90H)

The Read Manufacturer/Device ID command is for reading both the JEDEC assigned Manufacturer ID

and the specific Device ID. The command is initiated by driving the CS# pin low and shifting the command

code “90H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the

Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in

Figure11. If the 24-bit address is initially set to 000001H, the Device ID will be read first

.

Figure10. Chip Erase Sequence Diagram

Figure11. Read Manufacture ID/ Device ID Sequence Diagram