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SL28647CLC Datasheet(PDF) 6 Page - Silicon Laboratories

No. de pieza SL28647CLC
Descripción Electrónicos  Clock Generator for Intel짰CK505
PDF  27 Pages
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Fabricante Electrónico  SILABS [Silicon Laboratories]
Página de inicio  http://www.silabs.com
Logo SILABS - Silicon Laboratories

SL28647CLC Datasheet(HTML) 6 Page - Silicon Laboratories

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SL28647
.......................Document #: 001-05103 Rev *B Page 6 of 27
Byte 2 Control Register 2
Bit
@Pup
Name
Description
7
1
PCIF0_OE
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
6
1
27M_non_SS/DOT_96_OE 27M Non-spread and DOT_96 MHz Output Enable
0 = Disable, 1 = Enabled
5
1
48M_OE
48-MHz Output Enable
0 = Disabled, 1 = Enabled
4
1
REF0_OE
REF0 Output Enable
0 = Disabled, 1 = Enabled
3
1
REF1_OE
REF1 Output Enable
0 = Disabled, 1 = Enabled
2
1
CPU1_OE
CPU[T/C]1 Output Enable
0 = Disabled, 1 = Enabled
1
1
CPU0_OE
CPU[T/C]0 Output Enable
0 = Disabled, 1 = Enabled
0
1
CPU, SRC, PCI, PCIF
Spread Enable
PLL1 (CPU PLL) Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Byte 3 Control Register 3
Bit
@Pup
Name
Description
7
1
PCI4_OE
PCI4 Output Enable
0 = Disabled, 1 = Enabled
6
1
PCI3_OE
PCI3 Output Enable
0 = Disabled, 1 = Enabled
5
1
PCI2_OE
PCI2 Output Enable
0 = Disabled, 1 = Enabled
4
1
PCI1_OE
PCI1 Output Enable
0 = Disabled, 1 = Enabled
3
1
RESERVED
RESERVED
2
1
RESERVED
RESERVED
1
1
CPU2/SRC10_OE
CPU2/SRC10 Output Enable
0 = Disabled, 1 = Enabled
0
1
RESERVED
RESERVED
Byte 4 Control Register 4
Bit
@Pup
Name
Description
7
0
SRC7_STP_CTRL
Allow control of SRC7 with assertion of PCI_STP# or SW PCI_STP
0 = Free running, 1 = Stopped with PCI_STP#
6
0
SRC6_STP_CTRL
Allow control of SRC6 with assertion of PCI_STP# or SW PCI_STP
0 = Free running, 1 = Stopped with PCI_STP#
5
0
SRC5_STP_CTRL
Allow control of SRC5 with assertion of PCI_STP# or SW PCI_STP
0 = Free running, 1 = Stopped with PCI_STP#
4
0
SRC4_STP_CTRL
Allow control of SRC4 with assertion of PCI_STP# or SW PCI_STP
0 = Free running, 1 = Stopped with PCI_STP#
3
0
SRC3_STP_CTRL
Allow control of SRC3 with assertion of PCI_STP# or SW PCI_STP
0 = Free running, 1 = Stopped with PCI_STP#
2
0
SRC2_STP_CTRL
Allow control of SRC2 with assertion of PCI_STP# or SW PCI_STP
0 = Free running, 1 = Stopped with PCI_STP#
1
0
SRC1_STP_CTRL
Allow control of SRC1 with assertion of PCI_STP# or SW PCI_STP
0 = Free running, 1 = Stopped with PCI_STP#



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