CY8C52LP datasheet(35/114 Pages) CYPRESS

35 / 114 page

PSoC® 5LP: CY8C52LP Family

Datasheet

Document Number: 001-84933 Rev. *L

Page 35 of 114

6.4.1 Drive Modes

Each GPIO and SIO pin is individually configurable into one of

the eight drive modes listed in Table 6-6. Three configuration bits

are used for each pin (DM[2:0]) and set in the PRTxDM[2:0]

registers. Figure 6-12 depicts a simplified pin view based on

each of the eight drive modes. Table 6-6 shows the I/O pin’s drive

state based on the port data register value or digital array signal

if bypass mode is selected. Note that the actual I/O pin voltage

is determined by a combination of the selected drive mode and

the load at the pin. For example, if a GPIO pin is configured for

resistive pull up mode and driven high while the pin is floating,

the voltage measured at the pin is a high logic state. If the same

GPIO pin is externally tied to ground then the voltage

unmeasured at the pin is a low logic state.

Figure 6-12. Drive Mode

Table 6-6. Drive Modes

Diagram

Drive Mode

PRTxDM2

PRTxDM1

PRTxDM0

PRTxDR = 1

PRTxDR = 0

High impedance analog

High-Z

High Impedance digital

High-Z

Resistive pull-up[9]

Res High (5K)

Strong Low

Resistive pull-down[9]

Strong High

Res Low (5K)

Open drain, drives low

High-Z

Strong Low

Open drain, drive high

Strong High

High-Z

Strong drive

Strong High

Strong Low

Resistive pull-up and pull-down[9]

Res High (5K)

Res Low (5K)

Out

0. High Impedance

Analog

1. High Impedance

Digital

2. Resistive Pull-Up

3. Resistive Pull-Down

4. Open Drain,

Drives Low

5. Open Drain,

Drives High

6. Strong Drive

7. Resistive Pull-Up

and Pull-Down

VDD

The ‘Out’ connection is driven from either the Digital System (when the Digital Output terminal is connected) or the Data Register

(when HW connection is disabled).

The ‘In’ connection drives the Pin State register, and the Digital System if the Digital Input terminal is enabled and connected.

The ‘An’ connection connects to the Analog System.

Note

9. Resistive pull up and pull down are not available with SIO in regulated output mode.

CY8C52LP Datasheet(PDF) 35 Page - Cypress Semiconductor

CY8C52LP Datasheet(HTML) 35 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL