CY8C52LP datasheet(49/114 Pages) CYPRESS

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PSoC® 5LP: CY8C52LP Family

Datasheet

Document Number: 001-84933 Rev. *L

Page 49 of 114

8. Analog Subsystem

The analog programmable system creates application specific

combinations of both standard and advanced analog signal

processing blocks. These blocks are then interconnected to

each other and also to any pin on the device, providing a high

level of design flexibility and IP security. The features of the

analog subsystem are outlined here to provide an overview of

capabilities and architecture.



Flexible, configurable analog routing architecture provided by

analog globals, analog mux bus, and analog local buses



Successive approximation (SAR) ADC



One 8-bit DAC that provides either voltage or current output



Two comparators with optional connection to configurable LUT

outputs



CapSense subsystem to enable capacitive touch sensing



Precision reference for generating an accurate analog voltage

for internal analog blocks

Figure 8-1. Analog Subsystem Block Diagram

Analog

Interface

CMP

CapSense Subsystem

DSI

Array

Clock

Distribution

Decimator

Config &

Status

Registers

PHUB

CPU

Comparators

GPIO

Port

GPIO

Port

DAC

SAR

ADC

Precision

Reference

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