CY8C52LP datasheet(78/114 Pages) CYPRESS

78 / 114 page

PSoC® 5LP: CY8C52LP Family

Datasheet

Document Number: 001-84933 Rev. *L

Page 78 of 114

Figure 11-30. SAR ADC Noise Histogram, 1 msps, External

Reference

11.5.3 Analog Globals

100

Counts, 12 bit

Table 11-21. Analog Globals DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Rppag

Resistance pin-to-pin through

P2[4], AGL0, DSM INP, AGL1,

P2[5][43, 45]

VDDA = 3.0 V

–

1500

2200



VDDA = 1.71 V

–

1200

1700



Rppmuxbus

Resistance pin-to-pin through

P2[3], amuxbusL, P2[4][44, 45]

VDDA = 3.0 V

–

700

1100



VDDA = 1.71 V

–

600

900



Table 11-22. Analog Globals AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Inter-pair crosstalk for analog

routes[45]

106

––dB

BWag

Analog globals 3 db bandwidth[45] VDDA = 3.0 V, 25 °C

–

MHz

Notes

43. Based on device characterization (Not production tested).

44. The resistance of the analog global and analog mux bus is high if VDDA 2.7 V, and the chip is in either sleep or hibernate mode. Use of analog global and analog

mux bus under these conditions is not recommended.

45. Pin P6[4] to del-sig ADC input; calculated, not measured.

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