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AM652X Datasheet(PDF) 198 Page - Texas Instruments |
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AM652X Datasheet(HTML) 198 Page - Texas Instruments |
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198 / 299 page  SPI_CS[x] (OUT) SPI_SCLK (OUT) SPI_SCLK (OUT) SPI_D[x] (OUT) SPI_CS[x] (OUT) SPI_SCLK (OUT) SPI_SCLK (OUT) SPI_D[x] (OUT) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit0 PHA=0 EPOL=1 POL=0 POL=1 PHA=1 EPOL=1 POL=0 POL=1 SM8 SM9 SM6 SM3 SM1 SM2 SM1 SM8 SM9 SM3 SM1 SM2 SM1 SM6 SM7 SM6 SM2 SM3 SM2 SM3 SM6 SM6 SM6 SPRSP08_TIMING_McSPI_01 198 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2018, Texas Instruments Incorporated Figure 5-66. SPI Master Mode Transmit Timing 5.11.5.15.2 MCSPI—Slave Mode Table 5-63, Figure 5-67, and Figure 5-68 present Timing Requirements for SPI - Slave Mode. Table 5-63. Timing Requirements for SPI - Slave Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT SS1 tc(SPICLK) Cycle time, SPI_CLK 20.8 ns SS2 tw(SPICLKL) Typical Pulse duration, SPI_CLK low 0.45P(2) ns SS3 tw(SPICLKH) Typical Pulse duration, SPI_CLK high 0.45P(2) ns SS4 tsu(SIMO-SPICLK) Setup time, SPI_D[x] valid before SPI_CLK active edge 5 ns SS5 th(SPICLK-SIMO) Hold time, SPI_D[x] valid after SPI_CLK active edge 5 ns SS6 td(SPICLK-SOMI) Delay time, SPI_CLK active edge to mcspi_somi transition 2 5 ns SS7 tsk(CS-SOMI) Delay time, SPI_CS[x] active edge to mcspi_somi transition 20.95 ns SS8 tsu(CS-SPICLK) Setup time, SPI_CS[x] valid before SPI_CLK first edge 5 ns SS9 th(SPICLK-CS) Hold time, SPI_CS[x] valid after SPI_CLK last edge 5 ns |
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