MP7612

11

Rev. 3.00

A0 to A15

02

R/W

DBO to DB7

MC6800

8

16

E1

E3

E2

A0 to A2

3

16

8

74LS138

Address

Decoder

SDI

DB7

RST

LD

CLK

Data Bus

Address Bus

From SYSTEM RESET

NOTES

1.

Execute consecutive memory write instructions while manipulating the data between WRITEs so that each

WRITE presents the next bit.

2.

The serial data loading is triggered by the CLK pulse which is asserted by a decoded memory WRITE to

memory location 2000, R/W, and 02. A WRITE to address 4000 transfers data from input shift register to DAC

register.

Figure 7. MC6800 Interface

Figure 8. 8085 Interface

ALE

WR

SOD

8085

8212

8

8

8

Address Bus

Data Bus

+5

E1

E3

E2

A0 to A2

3

74LS138

Address

Decoder

SDI

LD

RST

CLK

From SYSTEM RESET

NOTES:

1.

Clock generated by WR and decoding address 8000.

2.

Data is clocked in the DAC shift register by executing memory write instructions. The clock input is generated

by decoding address 8000 and WR. Data is then loaded into the DAC register with a memory write instruction

to address 4000.

3.

Serial data must be present in the right justified format in registers H & L of the microprocessor.