MP7612

7

Rev. 3.00

A3

A2

A1

A0

D11

D10

D9

D8

D7

D6

D0

1

0

SDI

(Data In)

CLK

LD

SDO

Previous Data

DAC Register

Loaded

A3 (1)

1

0

1

0

1

0

Figure 1. Serial Data Timing and Loading

1

0

SDI

SDO

CLK

LD

HIGH Z

+1/2 LSB Band

RST

Figure 2. Serial Data Input Timing (RST = “1”)

1

0

1

0

1

0

+FS

–FS

1

+1/2 LSB Error Band

0

Figure 3. Reset Operation

Notes:

(1)

CLK should be high during the falling edge of LD to insure proper function of the shift register.

Notes:

(1)

Because A3 is available immediately after 16th clock edge of DATA Shift-in, only 15 clock cycles are needed to

complete the readback.

MSB