STR720 datasheet(365/401 Pages) STMICROELECTRONICS

365 / 401 page

STR720 - POWER REDUCTION MODES

365/401

After reset the RCCU is configured in RUN mode with PLL switched off, PLL_BYP enabled

and DIV2 disabled, so that the main system frequency at start-up is equal to CLK input. To

select the actual operating system frequency, the DIV2 multiplexer should be enabled first if

the input clock frequency requires it, then PLL should be switched on after having

programmed its multiplying factor. The signal generated by PLL can be selected as clock

source disabling the PLL_BYP multiplexer but this operation should be performed only when

PLL is stable (about 200

µs). A LOCK status bit can be used to detect PLL status and switch

to its clock only when lock condition is reached. Any change of PLL lock condition is registered

in dedicated interrupt pending flags. If application requires to take immediate actions when

PLL lock condition is lost or achieved, an automatic PLL bypass can be enforced each time

the lock condition changes, switching to reference clock as soon as lock condition is lost and

switching back to PLL clock when lock condition is regained. This mechanism can be enabled

by setting the AUTOBYP_EN flag.

The PLL should be switched-off before changing the multiply factor, using the reference clock

during this transitory phase.

For more detail about PLL management see Section 13.3.2: PLL Management on page 140.

During RUN mode, most of STR720 peripherals clocks can be independently switched on and

off using PCG registers inside A-APB bridge, CGC block registers and a few SGCR1 register

bits. In this way only the peripherals whose functionalities are required by the system need to

be clocked, so the actual power consumption of the whole STR720 device can be adapted by

software, according to application requirements and the exact current consumption is heavily

dependent on which blocks are active and for how long. At system reset all of controlled

peripherals are kept under reset with their clock signals switched off, except EIC, EMI and

DRAMC which are required for system start-up. It is up to application software to enable the

required peripherals. The following table summarizes the peripherals whose clock and reset

lines can be controlled:

29 / 8

58.00

3.63

29.00

15 / 4

60.00

3.75

30.00

31 / 8

62.00

3.88

31.00

8 / 2

64.00

4.00

32.00

33 / 8

66.00

4.13

33.00

17 / 4

68.00

4.25

34.00

22.67

35 / 8

70.00

4.38

35.00

23.33

Table 82. RUN mode system frequencies (CLK=16 MHz)

PLL Multiplier / Divider

AHB / S-APB

[MHz]

A-APB min

(f/16)

A-APB max

(f/2)

ATAPI

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