STR720 datasheet(367/401 Pages) STMICROELECTRONICS

367 / 401 page

STR720 - POWER REDUCTION MODES

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25.2 IDLE Mode

In this operating mode, main system clock is derived from CLK input dividing it by 32. In this

way the whole system can still evolve, although at a very low rate, but power consumption will

be greatly reduced. Any setting for A-APB and ATAPI clock generation remains unchanged

even if proper operation of the peripheral subsystem cannot be maintained due to the reduced

operating frequency.

Application software can switch off any peripheral not required in this operating mode as

much as disabling the PLL (see Section 13.3.2: PLL Management on page 140) and any

other analog part whose functionality is not required. If for example an external clock of

16 MHz is applied to CLK input, activating this operating mode results in a system frequency

(AHB/S-APB clock) being either 250 kHz or 500 kHz, depending if DIV2 multiplexer is enabled

or not.

No particular sequence must be used to enter or exit IDLE mode since interrupt detection is

always active; only the external SDRAM banks should be put in self-refresh mode before

entering IDLE mode, otherwise their contents will be lost due to the very long refresh interval.

Once in self-refresh mode, SDRAMC clock can be switched off safely.

25.3 SLOW Mode

In this operating mode, main system clock is taken directly from OSCIN pad, where the

32 kHz oscillator used to supply RTC is connected. In this way system operations are virtually

frozen due to the extremely low rate system frequency.

As it happens in IDLE mode, any setting for A-APB and ATAPI clocks is not affected by

entering in SLOW mode, so application software is responsible for switching off any part of the

system which is not strictly required, especially the analog parts: PLL, ADC and also clock

input receivers since main clock signal detection is not required in this mode, being based on

the 32 kHz oscillator.

Note

Before entering SLOW mode the A-APB clock frequency should be set to be AHB

clock divided by 2 if the watchdog is configured to use the external low frequency

clock source due to internal synchronization requirements of this clock signal which

is derived from the same 32 kHz oscillator.

It must be noticed that when main clock is switched off also at the application board level,

particular care must be observed when generating internal reset events (watchdog or

software triggered) since the absence of that external clock prevents the correct

synchronization of the internal reset signal deassertion. As a consequence when main

external clock is switched off on the board, watchdog should be disabled or used as a plain

timer and no software reset should be issued, since in both cases the exit from these reset

events would not be properly synchronized. In case a software reset is required, main board

clock should be restarted before generating it.

STR720 Datasheet(PDF) 367 Page - STMicroelectronics