STR720 datasheet(368/401 Pages) STMICROELECTRONICS

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STR720 - POWER REDUCTION MODES

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No other particular care must be used to enter or exit SLOW mode, although the same

consideration mentioned in IDLE mode section about external SDRAM banks and DRAMC

should be applied as well.

25.4 STOP Mode

When it is required that system configuration is preserved without feeding any clock to the

system, the STOP mode functionality can be used, where only RTC section remains clocked

and the rest of the system is completely frozen, thus reducing its consumption to the leakage

current only. Upon entering STOP mode, a specific sequence must be executed by application

software in order to leave the system in a state where consumption is minimum but it is still

possible to wake the system up without resetting it and thus altering previous data and

configuration. The code to enter STOP mode should be written according to the following

rough sequence:

1. Switch off operation of all analog sections.

2. Enter SLOW mode. As a consequence system clock is now 32 kHz.

3. Switch off PLL to remove its power consumption (see Section 13.3.2: PLL Management

on page 140).

4. Disable STOP mode, clearing bit STOP_EN in RCCU MSKCTL register, so that system

remains alive even after WIU block rises STOP mode request.

5. Mask wake-up request from CLK clock line, clearing bit 7 in WIU WUMR register. This is

to be sure that the CLK clock, which is still active at this time, cannot exit immediately from

STOP mode.

6. Issue the STOP sequence described in WIU section (See “WAKE-UP INTERRUPT UNIT

(WIU)” on page 70.). After this sequence is completed, the STOP_REQ signal is activated

so RCCU will be ready to stop main clock signal. External devices can be notified that

STR720 is about to enter STOP mode by using the alternate function associated to P3.7

pad, so that they can react accordingly, for example switching off CLK clock source.

7. If application does not require to use the activity on CLK clock line as wake-up event,

STOP mode could be entered now, jumping to step 9.

Otherwise it is necessary to poll bit 7 in WIU WUPR register, each time clearing the bit,

until it is read as ‘0’, meaning that no more activity is present on CLK clock line.

8. The wake-up request corresponding to CLK clock line can now be unmasked, setting to

‘1’ bit 7 in WIU WUMR register.

9. STOP mode can now be enabled, setting bit STOP_EN in RCCU MSKCTL register. From

now on main system clock is frozen.

Note

The change of PLL lock condition, associated to interrupt/wake-up line number 6,

cannot be used as wake-up event. Selecting this input as the only wake-up source

will stuck the system so as only a reset event can restore normal operations.

WARNING: Whenever a STOP request is issued to the system, a few clock cycles are needed

to actually enter STOP mode. Hence the execution of the instruction following the setting of

STOP_EN bit in RCCU might start before entering STOP mode (consider the ARM7

three-stage pipeline as well). In order to avoid to execute any valid instruction after a correct

STOP sequence and before entering the STOP mode, it is mandatory to execute a dummy set

of few instructions after the setting of STOP_EN bit. In particular at least six dummy

instructions (e.g. MOV R1, R1) shall be added after the end of STOP sequence. Again, if

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