STR720 datasheet(369/401 Pages) STMICROELECTRONICS

369 / 401 page

STR720 - POWER REDUCTION MODES

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exiting from STOP mode an interrupt routine shall be serviced, another set of dummy

instructions shall be added, to take into account of the latency period: this is evaluated in at

least other three dummy instructions. This to consider that when STOP mode entered, the

pipeline content is frozen as well, and when the system restarts the first executed instruction

was fetched and decoded before entering the STOP mode itself.

Exiting STOP mode can be triggered by two different sets of events: internal events generated

on some STR720 peripheral pins (as UART reception line or USB wake-up signalling) or

external events restoring CLK clock line. All these events can be detected by WIU which will

deactivate the STOP_REQ signal as a response, thus removing the STOP condition from

RCCU block. A guideline to write the code required to exit STOP mode can be the following:

1. Upon wake-up event, WIU removes STOP_REQ signal notifying to the external devices

that STR720 is about to exit STOP mode. If the traced event is triggered by STR720

peripherals, this signal will be used by a possible external power manager to restore CLK

clock otherwise it will have been CLK clock activity, restarted autonomously by the exter-

nal power manager, which triggered STR720 wake-up.

2. STOP_REQ deactivation restarts RCCU operations, which awakes system clock in SLOW

mode.

3. Application software should now determine which wake-up source triggered the exit from

STOP mode, in order to take any consequent action. If CLK clock activity is not there (see

point 7 of previous sequence), a system dependent time interval must be waited so to

allow a stable CLK clock to be present on STR720 pads.

4. RCCU can now be switched back in RUN mode, the PLL enabled again and all the rest of

system operation restored.

25.5 STANDBY Mode

The minimum level of power consumption can be reached using STANDBY mode, where not

only main system clocks are stopped but also main power supply is removed from STR720

device, except the RTC section with its 32 kHz oscillator, so that time can be still traced while

most of the system is kept under reset condition. This extreme power saving mode can be

exited re-initializing the whole device using RSTIN pad, thus losing any previous state and

configuration while the real time clock counter is not affected.

Any action required by the system to enter safely STANDBY mode has to be performed by

application software, following a request arrived from an external power manager and

acknowledging the enter in STANDBY mode after having saved any required state information

into an external storage area (for example an external FLASH device). A pair of GPIO pins

can be used to implement this protocol. As a response to STR720 entering in STANDBY

mode, the external power manager should activate RSTIN pad and then remove VDD supply,

leaving only VDDRTC active.

When the external power manager requires STR720 to exit STANDBY mode, it should restore

VDD supply to its nominal value always keeping RSTIN pad driven low so that a safe hardware

reset sequence is triggered, and only after VDD supply is stable to its nominal value, RSTIN

pad should be raised again. STR720 will start a reset sequence, eventually restoring its

previous state using the informations saved into the external storage area, and system

operation can restart.

STR720 Datasheet(PDF) 369 Page - STMicroelectronics

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