MMA8652FC datasheet(54/65 Pages) NXP

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MMA8652FC

Sensors

Freescale Semiconductor, Inc.

6.12.2

0x2B: CTRL_REG2 System Control 2 register

CTRL_REG2 register is used to enable Self-Test, Software Reset, and Auto-SLEEP. In addition, it enables you to configure the

SLEEP and WAKE mode power scheme selection (oversampling modes).

When the reset bit is enabled, all registers are reset and are loaded with default values. Writing ‘1’ to the RST bit immediately

resets the device, no matter whether it is in ACTIVE/WAKE, ACTIVE/SLEEP, or STANDBY mode.

The I2C communication system is reset to avoid accidental corrupted data access.

At the end of the boot process the RST bit is deasserted to 0. Reading this bit will return a value of zero.

The (S)MODS[1:0] bits select which Oversampling mode is to be used, as shown in Table 100. The Oversampling modes are

available in both WAKE Mode MOD[1:0] and also in the SLEEP Mode SMOD[1:0].

Table 98. 0x2B CTRL_REG2 register (Read/Write)

Back to Register Address Map

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RST

SMODS1

SMODS0

SLPE

MODS1

MODS0

Table 99. CTRL_REG2 register

Bit(s)

Field

Description

7ST

Self-Test Enable

Activates the self-test function.

• When ST is set, the X, Y, and Z outputs will shift.

0 Self-Test disabled (default)

1 Self-Test enabled

6RST

Software Reset

RST bit is used to activate the software reset.

• The reset mechanism is enabled in both STANDBY and ACTIVE modes.

0 Device reset disabled (default)

1 Device reset enabled.

4–3

SMODS[1:0]

SLEEP mode power scheme selection

See Table 100 and Table 101

00 (default)

2SLPE

Auto-SLEEP enable

0 Auto-SLEEP is not enabled (default)

1 Auto-SLEEP is enabled.

1–0

MODS[1:0]

ACTIVE mode power scheme selection

See Table 100 and Table 101

00 (default)

Table 100. (S)MODS Oversampling modes

(S)MODS1

(S)MODS0

Power Mode

Normal

Low Noise Low Power

High Resolution

Low Power

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