ADC32RF83 datasheet(66/138 Pages) TI

No. de pieza	ADC32RF83

Descripción Electrónicos	ADC32RF8x Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices

PDF	138 Pages

Scroll/Zoom	100%

Fabricante Electrónico	TI [Texas Instruments]

Página de inicio	http://www.ti.com

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66 / 138 page

R/W

SDIN

SCLK

SEN

RESET

A11

A10

ADC32RF80, ADC32RF83

SBAS774A – MAY 2016 – REVISED DECEMBER 2016

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Product Folder Links: ADC32RF80 ADC32RF83

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3. Writing into the desired register by setting both the M bit and P bit to 1. Write register content. When a page

is selected, multiple writes into the same page can be done. Addressing in an SPI cycle begins with 6xxx

when selecting a page from the digital bank because the M bit must be set to 1, as shown in Figure 140.

Note that the JESD digital page is common for both channels. The CH bit can be used to distinguish

between two channels when programming registers in the JESD digital page. When CH = 0, registers are

programmed for channel B; when CH = 1, registers are programmed for channel A. Thus, an SPI cycle to

program registers for channel B begins with 6xxx and channel A begins with 7xxx.

Figure 140. SPI Write Timing Diagram for Digital Bank Register Write

ADC32RF83 Datasheet(PDF) 66 Page - Texas Instruments