AD9546SLASHPCBZ datasheet(140/205 Pages) AD

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AD9546

Data Sheet

Rev. 0 | Page 140 of 205

TIME STAMP TAGGING OPTIONS

The input to the DPLL consists of time stamps arriving from

two TDCs: a reference input TDC and a feedback TDC.

Furthermore, the user can enable tagging of time stamps

originating from those TDCs (see the Tagged Time Stamps

section). The user can also enable the DPLL to operate based on

tagged time stamps (rather than every time stamp) originating

from the reference and/or feedback TDCs.

The use of tagged time stamps by the DPLL only applies for zero

delay (hitless) mode. The DPLL ignores tagged time stamps in

phase buildout mode. See the Frequency Translation Loops section

for an explanation of zero delay and phase buildout modes.

The user establishes the tagged time stamp functionality of the

DPLL via Bits[4:2] of the appropriate translation profile at the

start address shown in Table 74 plus an offset of 3 (decimal).

There are five tagged operating modes per Table 86.

Table 86. Tagged Time Stamp Operating Modes

Bits[4:2]

Tag Mode

No tagging (default)

Reference tagging only

Feedback tagging only

Combined reference and feedback tagging with

equal carrier rates

Combined reference and feedback tagging with

unequal carrier rates

5 to 7

Not applicable

With respect to tagged time stamps, the carrier rate is the rate at

which the TDC generates time stamps (that is, the underlying rate

of the input clock to the TDC). The tagged rate is the rate at which

the TDC generates tagged time stamps. The tagged rate is

always an integer submultiple of the carrier rate.

The no tagging mode is the normal operating mode of the DPLL.

That is, the digital PFD processes every reference and feedback

time stamp whether the time stamp is a tagged time stamp or not.

The reference tagging only mode tells the digital PFD to use

tagged reference time stamps for phase alignment purposes.

The user must ensure the reference is set up to provide tagged

time stamps. When the reference is one of the REFx or auxiliary

REFx inputs, the reference demodulator is the source of tagged

time stamps (see the Reference Demodulator section). When

the reference is an auxiliary NCO, the auxiliary NCO is the

source of tagged time stamps (see the Auxiliary NCOs section).

The feedback tagging only mode tells the digital PFD to use

tagged feedback time stamps for phase alignment purposes.

The user must ensure the feedback path is set up to provide

tagged time stamps via output clock modulation (see the

Distribution Embedded Output Clock Modulation section).

The combined reference and feedback tagging modes tell the

digital PFD to use tagged time stamps from both the reference

and feedback TDCs. The user must ensure that the reference

and feedback paths are set up to provide tagged time stamps.

Furthermore, the user must ensure that the tag rate of the

reference path matches the tag rate of the feedback path.

There are two variants of the combined reference and feedback

tagging modes: equal and unequal carrier rates. The combined

reference and feedback tagging modes require equal tag rates

on both paths. There is no such requirement on the carrier

rates for both paths. However, to function properly, the DPLL

requires advance knowledge of the relationship between the

reference and feedback carrier rates, which is the reason for the

two variants. The user must select the appropriate variant based

on whether the reference and feedback TDC carrier rates differ.

AD9546/PCBZ Datasheet(PDF) 140 Page - Analog Devices

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