AD9546SLASHPCBZ datasheet(144/205 Pages) AD

144 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 144 of 205

ANALOG PLL (APLL)

APLL OVERVIEW

Figure 100 shows a block diagram of the APLL, which is valid

for both APLL0 and APLL1. The main components of the

APLL comprise the following:

•

An integrated VCO

•

A combined PFD and charge pump

•

A loop filter

•

A feedback divider (M divider)

The purpose of the APLL is

•

To provide a low noise output clock signal

•

To upconvert the DPLL output frequency to ~3 GHz

•

To suppress the spurious artifacts of the NCO

VOLTAGE CONTROLLED OSCILLATOR (VCO)

The VCO provides a spurious free, low noise RF clock signal in

the 3 GHz range that feeds the output distribution section, with

APLL0 as the source for the OUT0x outputs and APLL1 as the

source for the OUT1x outputs. The VCOs for APLL0 and

APLL1 cover nonoverlapping frequency ranges, as shown in

Table 87. The output frequency of the APPL is one half of the

VCO frequency due to the P divider (see Figure 100).

Table 87. APLL VCO Frequency and Gain

APLL

VCO Frequency (MHz)

VCO Gain (MHz/V)

2424 to 3232

3232 to 4040

100

The VCO has a frequency range that is approximately

800 MHz, which consists of many narrow, overlapping

frequency bands. To ensure the VCO uses the appropriate band

for a given output frequency and to accommodate proper

operation over a broad temperature range, the AD9546

incorporates an automated VCO calibration feature.

VCO Calibration

To initiate VCO calibration of APLL0 or APLL1 independently,

write a Logic 1 to Bit 1 of Register 0x2100 (for APLL0) and

Therefore, the user must immediately restore Bit 0 to Logic 0,

because maintaining a static Logic 1 state may cause unexpected

device behavior.

To calibrate both APLL channels together, instead of each channel

independently, write a Logic 1 to Bit 1 of Register 0x2000. Bit 1

calibrates the system clock PLL as well as both APLLs.

One option for checking the status of the APLL VCO calibration

process is via Bits[5:4] of Register 0x3100 (for APPL0) and

APPL is busy calibrating. Bit 5, when Logic 1, indicates the

APPL is done calibrating. Bit 4 is also available as a physical

output signal via an appropriately configured Mx pin.

The other option for checking the status of the APLL VCO

calibration process is via Bits[1:0] of Register 0x3014 (for APLL0)

and Register 0x3019 (for APLL1). Because Bit 0 and Bit 1

represent the latched state transitions of Bit 4 and Bit 5,

respectively, they may represent a condition that is no longer

true. Therefore, the user must clear Bit 0 and Bit 1 via Bit 0 and

Bit 1, respectively, of Register 0x200F for APLL0 and Register

0x2014 for APLL1. Otherwise, the user may lose indication of

subsequent state changes of the VCO calibration process.

PHASE

DETECTOR AND

CHARGE PUMP

VCO

CAL

LOCK

DETECTOR

LFx

LDOx

AD9546

VCO

LOOP FILTER

OUTPUT

DISTRIBUTION

CHARGE

PUMP

CONTROL

LOOP

FILTER

CONTROL

3.9nF

P DIVIDER

REG 0x1080, BITS[6:0]

REG 0x3100, BIT 4

REG 0x3100, BIT 5

REG 0x3014, BIT 0

REG 0x3014, BIT 1

220nF

÷2

NOTES

1. A RANGE OF ADDRESSES OR BITS USES A COLON SEPARATOR

2. REGISTER ADDRESSES ARE SPECIFIC TO APLL0

REG 0x1080, BIT 7

REG 0x1083, BIT 0

REG 0x1083, BITS[2:1]

REG 0x1083, BIT 3

REG 0x1082, BITS[1:0]

REG 0x1082, BITS[4:2]

REG 0x1082, BITS[7:5]

REG 0x2100, BIT 1

REG 0x1081,

BITS[7:0]

REG 0x3100, BIT 3

REG 0x3014, BIT 2

REG 0x3014, BIT 3

Figure 100. APLL Block Diagram

AD9546/PCBZ Datasheet(PDF) 144 Page - Analog Devices

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