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AD9546/PCBZ Datasheet(PDF) 142 Page - Analog Devices

No. de pieza AD9546/PCBZ
Descripción Electrónicos  Dual DPLL Digitized Clock Synchronizer
PDF  205 Pages
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
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AD9546/PCBZ Datasheet(HTML) 142 Page - Analog Devices

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AD9546
Data Sheet
Rev. 0 | Page 142 of 205
Figure 99 shows cascaded DPLL configuration and its operation.
The main difference between Figure 98 and Figure 99 is that
DPLL1 has Translation Profile 1.x configured to use the
feedback path of DPLL0 as a reference input. Setting up
Translation Profile 1.x in this way establishes the potential for
cascaded DPLL operation. The fact that Translation Profile 1.x
is set up to use the feedback path of DPLL0 as a reference input
identifies DPLL1 as the secondary DPLL and DPLL0 as the
primary DPLL in the cascaded DPLL configuration (see the
right side of Figure 99).
The existence of Translation Profile 1.x is one of two conditions
necessary to enable cascaded DPLL operation. The other
condition is that the primary DPLL must have an assigned
inactive profile. The user makes this assignment via Bits[2:0] of
Register 0x102A (for DPLL0) or Register 0x142A (for DPLL1). By
default, Bits[2:0] = 000 (binary), which assigns Translation
Profile 0.0 (for DPLL0) or Translation Profile 1.0 (for DPLL1)
as the inactive profile assignment, but the user can specify any
one of the six translation profiles as the inactive profile via
Bits[2:0]. Programming Bits[2:0] with a value of x, where x is 0
to 5 (decimal) selects the corresponding Translation Profile 0.x
or 1.x, where x can be any integer value from 0 to 5). Figure 99
indicates Translation Profile 0.b as the inactive profile to
demonstrate a nondefault example.
Consider the left side of Figure 99, which is the same as in
Figure 98 except for the fact that DPLL0 has Translation Profile B
assigned as its inactive profile. Like Figure 98, both DPLLs lock
to Reference Source 1. The middle portion of Figure 99 applies
when Reference Source 1 is lost. Like Figure 98, both DPLLs
lock to Reference Source 2. When Reference Source 2 is lost (as
shown in the right portion of Figure 99), however, and
assuming the user has configured a translation profile
(Translation Profile 1.x in this example) to use the feedback
path of the primary DPLL as a reference source, the following
events occur.
When DPLL0 loses its reference, it has no recourse but to
switch to holdover or freerun mode because no reference
sources are available. However, when Translation Profile 0.b
becomes inactive, because Translation Profile B is the inactive
profile index for DPLL0, the feedback path of the DPLL0 is
available as a valid reference for DPLL1. Although DPLL0
switches to holdover or freerun, DPLL1 does not because it has
an available reference source: the feedback path of DPLL0.
DPLL1 may experience a momentary switch to holdover or
freerun mode before switching to cascaded DPLL operation.
The result is cascaded DPLL operation, in which the reference
input of DPLL1 (the secondary DPLL) connects to the feedback
path of DPLL0 (the primary DPLL). In this way, the two DPLL
outputs are phase locked, which preserves the original
requirement of phase locked DPLL outputs even when all
reference sources are lost.
The role of the primary and secondary DPLLs is reversible
because the role is dependent on how the user programs the
translation profiles and assigns the inactive profile index.
For the cascaded DPLL configuration to become active, the
following conditions are necessary:
A translation profile associated with the secondary DPLL
that assigns the feedback path of the primary DPLL as a
reference input must exist.
The primary DPLL must have an inactive translation
profile assignment (by default, the inactive profile is
Translation Profile 0 unless otherwise specified).
The primary channel of the APLL must be calibrated and
indicate locked status.
The primary DPLL must be inactive, that is, either in
freerun or holdover operation.
DIGITAL
CROSS
POINT
MUX
TO
APLL0
TO
APLL0
PFD
LF
NCO
N
DPLL0
PFD
LF
NCO
N
DPLL1
TO
APLL1
REFERENCE
SOURCE 1
LOST
TO
APLL0
NCO
DPLL0
DPLL1
FTW
TRANSLATION
PROFILE 0.a
TRANSLATION
PROFILE 1.z
PFD
LF
NCO
N
DPLL0
PFD
LF
NCO
N
DPLL1
TO
APLL1
TO
APLL1
TRANSLATION
PROFILE 0.b
TRANSLATION
PROFILE 1.y
ALL
REFERENCE
SOURCES
LOST
DIGITAL
CROSS
POINT
MUX
DIGITAL
CROSS
POINT
MUX
PROFILE B IS NOW
INACTIVE, BUT DPLL0
BECOMES A VALID
REFERENCE SOURCE BY
VIRTUE OF THE INACTIVE
INDEX ASSIGNMENT
N
PFD
LF
NCO
N
DPLL1 USES DPLL0 AS A
REFERENCE SOURCE
(DEFINED IN PROFILE 1.x)
TRANSLATION
PROFILE 1.x
DPLL0
CONFIGURED
WITH
INACTIVE
INDEX
ASSIGNED TO
PROFILE B
(PRIMARY)
(SECONDARY)
TDC
2
REFERENCE
SOURCES
TDC
1
TDC
2
REFERENCE
SOURCES
TRANSLATION PROFILE 0.a AND
TRANSLATION PROFILE 1.z ASSIGN
REFERENCE SOURCE 1
TRANSLATION PROFILE 0.b AND
TRANSLATION PROFILE 1.y ASSIGN
REFERENCE SOURCE 2
Figure 99. Cascaded DPLL Configuration



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