AD9546SLASHPCBZ datasheet(145/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 145 of 205

APLL FEEDBACK DIVIDER (M DIVIDER)

The user programs the APLL feedback M divider via Bits[7:0] in

The divide ratio of the M divider is the decimal value of

Bits[7:0], yielding divide ratios from 1 to 255. A value of 0 is the

same as 1.

For example, given a desired divide ratio of 27, program

Bits[7:0] = 27 (decimal) or 0x1B (hexadecimal).

PHASE FREQUENCY DETECTOR (PFD)

The PFD detects the instantaneous phase error between the

feedback signal from the M divider and the output from the

DPLL. The phase error essentially drives the servo loop of the

APLL in a manner that ultimately nulls out the phase difference

between the two signals. The PFD bandwidth is wide enough to

handle signals originating from the NCO of the DPLL (up to

~350 MHz nominal).

The APLLs incorporate lock detection circuitry that indicates

when they achieve a frequency locked condition. Locked status

indication is available via Bit 3 of Register 0x3100 (for APLL0)

and Register 0x3200 (for APLL1), where Logic 1 indicates

locked status. Bit 3 is also available as a physical output signal

via an appropriately configured Mx pin.

The IRQ section of the register map provides latched status bits

reflecting state transitions of the lock detector status via

Bits[3:2] of Register 0x3014 (for APLL0) and Register 0x3019 (for

APLL1). Bit 2 latches to Logic 1 on an unlocked to locked state

transition, whereas Bit 3 latches to Logic 1 on a locked to

unlocked state transition. Because Bit 2 and Bit 3 are latched

bits, the user must clear Bit 2 and Bit 3 via Bit 2 and Bit 3,

respectively, of Register 0x200F (for APLL0) and Register

0x2014 (APLL1). Otherwise, the user may lose indication of

subsequent state changes of the lock detector.

CHARGE PUMP

The charge pump consists of a pair of constant current sources

that deliver charge to or remove charge from the loop filter

based on the output of the phase detector. The transfer of

charge increases or decreases the voltage applied to the VCO,

which steers the VCO frequency to match the input frequency

and ultimately bring about a phase locked condition.

The charge pump has two operating modes, manual and

automatic, selectable via Bit 7 of Register 0x1080 (for APLL0)

and Register 0x1480 (for APLL1). Logic 1 (default) selects

manual mode, whereas Logic 0 selects automatic mode.

In manual mode, the user programs the charge pump current via

Bits[6:0] (unsigned) of Register 0x1080 and Register 0x1480.

The actual charge pump current (ICP) relates to Bits[6:0] (charge

pump scale) as follows:

ICP = Charge Pump Scale × 8 µA

(23)

ICP has a range of 0 µA to 1016 µA. The default value of

Bits[6:0] is 0x14 (20 decimal), which yields ICP = 160 µA.

For example, given ICP = 743 µA, determine the charge pump scale

value. Solving Equation 23 for the charge pump scale yields

Charge Pump Scale = ICP/8 µA

= 743 µA/8 µA

= 93 (nearest integer)

= 0x5D (hexadecimal)

In automatic mode, the charge pump current scale value is

ineffective. Instead, the APLL automatically adjusts the charge

pump current (ICP) based on the value of the M divider

according to Table 88. This automatic adjustment yields a

relatively constant loop bandwidth for M divider values from

1 to 63. The loop bandwidth is ~250 kHz for APLL0 and

~300 kHz for APLL1. Note that automatic charge pump control is

only valid over a subset of M divider values. Given this

constraint, it is generally best practice to avoid automatic mode.

Table 88. APLL Charge Pump Current in Automatic Mode

M Divider Value

ICP (µA)

1 to 63

M × 16

64 to 255

1016

Regardless of the operating mode (manual or automatic), the

charge pump has a provision for applying a constant dc offset

current to the output of the charge pump. Injection of an offset

current overcomes some of the spectral artifacts associated with

charge pump nonlinearity when the APLL is in a locked state.

Generally, noise performance improves significantly when this

feature is active and properly adjusted.

To enable or disable the dc offset current feature, use Bit 0 of

Logic 1 (default) enables this feature, whereas Logic 0 disables it.

To control the polarity (positive or negative) of the offset current,

use Bit 3 of Register 0x1083 (for APLL0) and Register 0x1483

(for APLL1). Logic 0 (default) is positive, whereas Logic 1 is

negative. The magnitude of the offset current depends on the

value of Bits[2:1] (unsigned) of Register 0x1083 (for APLL0)

and Register 0x1483 (for APLL1). The value of this bit field sets

the dc offset current as a fraction of ICP per Table 89, but with a

granularity of 8 µA. Thus, the offset current is in integer steps of

8 µA, with fractions of an 8 µA step rounded in the direction of

zero (that is, −53 µA rounds to −48 µA).

Table 89. APLL Charge Pump DC Offset Current

Bits[2:1] (Decimal)

DC Offset Current (% of ICP)

25 (default)

12.5

6.25

In general, the default values of the dc offset current and charge

pump scale yield optimal overall performance. For this reason, the

recommendation is to use only the manual charge pump mode

(refer to the Charge Pump section regarding manual charge

pump mode).

AD9546/PCBZ Datasheet(PDF) 145 Page - Analog Devices

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