AD9546SLASHPCBZ datasheet(147/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 147 of 205

REFERENCE SWITCHING

REFERENCE SWITCHING OVERVIEW

The AD9546 has a sophisticated reference switching mechanism

administered by an internal controller. In general, the DPLL

operates in closed-loop mode, wherein the DPLL locks to the

frequency and phase of a reference input signal. However, if a

reference becomes invalid, the AD9546 can automatically

switch to a different reference input, depending on how the

user programs translation profiles (see the Translation Profiles

section). In the absence of any valid references, the AD9546

switches to one of the two open-loop operating modes:

holdover or freerun. The DPLL selects freerun, holdover, or

manual/automatic source selection per the DPLL mode

selection flowchart of Figure 102. The three procedures in

Figure 102 (holdover, translation profile validation, and

priority-based translation profile selection) have separate flow

charts per Figure 103, Figure 104, and Figure 105, respectively.

The DPLL has three status indicators to notify the user when

the DPLL begins the switch to a new translation profile

(inferring a new reference input) or when the DPLL enters

freerun or holdover mode. These indicators reside in Bits[2:0]

of Register 0x3101 and Register 0x3201, as follows:

•

Bit 2: switching translation profiles

•

Bit 1: holdover mode

•

Bit 0: freerun mode

These indicators also inform corresponding IRQ status bits via

Bits[7:5] of Register 0x3011 and Register 0x3016, as follows:

•

Bit 7: switched translation profiles

•

Bit 6: entered freerun mode

•

Bit 5: entered holdover mode

Bit 7 latches to Logic 1 when the DPLL is in the process of

switching to an active translation profile. Bit 6 latches to Logic

1 when the DPLL enters freerun mode. Bit 5 latches to Logic 1

when the DPLL enters holdover mode. Because Bits[7:5] are

latched bits, the user must clear them via Bits[7:5] of Register

0x200C and Register 0x2011 to obtain visibility of subsequent

state transitions to reference switching, freerun, or holdover

(see the Interrupt Request (IRQ) section).

FORCED FREERUN MODE

Although the automatic reference switching capability of the

AD9546 can cause the DPLL to switch to freerun mode, the

user can force the DPLL to freerun mode by writing Logic 1 to

Bit 0 of Register 0x2105 (DPLL0) or Register 0x2205 (DPLL1).

In freerun mode, the DPLL operates open loop and produces a

static output frequency as dictated by the 46-bit freerun tuning

word in Register 0x1000 to Register 0x1005 (DPLL0) and

Freerun Tuning Word section for details.

FORCED HOLDOVER MODE

Although the automatic reference switching capability of the

AD9546 can cause the DPLL to switch to holdover mode, the

user can force the DPLL to holdover mode by writing Logic 1 to

Bit 1 of Register 0x2105 (DPLL0) or Register 0x2205 (DPLL1).

In holdover mode, like freerun mode, the DPLL operates open

loop and produces a static output frequency. However, the

DPLL uses one of three static tuning words dictated by the

tuning word history processor (see the Tuning Word History

section). Figure 103 shows a summary of the holdover tuning

word selection.

Note that freerun mode overrides holdover mode (see Figure 102).

Furthermore, freerun mode and holdover mode both override

the manual/automatic source selection modes (see the

Manual/Automatic Translation Profile Selection section).

MANUAL/AUTOMATIC TRANSLATION PROFILE

SELECTION

Assuming Bits[1:0] = 1 decimal in Register 0x2105 (DPLL0) or

based on Bits[3:2] of Register 0x2105 (DPLL0) or

profile selection modes per Table 91.

Table 91. DPLL Translation Profile Select Mode Settings

Bits[3:2]

(Decimal)

Description

Automatic, priority-based translation profile

selection

Manual translation profile selection with fallback

to priority-based translation profile selection

Manual translation profile selection with fallback

to holdover

Manual only translation profile selection

Manual Only Translation Profile Selection

The manual only translation profile selection mode in Table 91

(Bits[3:2] = 3 decimal) is not a recommended operating mode

because this setting includes several operational caveats.

Contact Analog Devices for application support on using the

manual only translation profile selection mode.

Manual Translation Profile Selection with Fallback to

Holdover

In the manual translation profile selection with fallback to

holdover mode (Bits[3:2] = 2 decimal), the user specifies a

particular translation profile for manual operation using

Bits[6:4] of Register 0x2105 (DPLL0) or 0x2205 (DPLL1). The

decimal value, y, of Bits[6:4] identifies the desired translation

profile, x.y (y is 0 to 5 and x is 0 or 1 for DPLL0 or DPLL1,

respectively). If the specified translation profile is not valid, the

DPLL switches to holdover operation (open loop). However,

depending on the status of the tuning word history processor

(see the Tuning Word History section), the DPLL may select

freerun operation instead of holdover.

AD9546/PCBZ Datasheet(PDF) 147 Page - Analog Devices

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