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AD9546/PCBZ Datasheet(PDF) 151 Page - Analog Devices

No. de pieza AD9546/PCBZ
Descripción Electrónicos  Dual DPLL Digitized Clock Synchronizer
PDF  205 Pages
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD9546/PCBZ Datasheet(HTML) 151 Page - Analog Devices

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Data Sheet
AD9546
Rev. 0 | Page 151 of 205
YES
NO
REG 0x3102,
BIT 0
= 1?
HOLDOVER
PROCEDURE
YES
NO
REG 0x100E,
BIT 1
= 1?
HISTORY
AVAILABLE
SINGLE
SAMPLE
HISTORY
DPLL USES MOST
RECENT TUNING WORD
DPLL USES
REG 0x1005:0x1000,
BITS[45:0]
FREERUN
REG 0x3108:0x3103,
BITS[45:0]
HISTORY
ENTER
EXIT
NOTES
1. A RANGE OF ADDRESSES OR BITS USES A COLON SEPARATOR
2. REGISTER ADDRESSES ARE SPECIFIC TO DPLL0
DPLL USES
Figure 103. Holdover Flowchart



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