AD9546SLASHPCBZ datasheet(152/205 Pages) AD

152 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 152 of 205

TRANSLATION PROFILE

VALIDATION PROCEDURE

YES

REG 0x3001,

BIT 1

= 1?

TRANSLATION

PROFILE 0.2

ENABLED?

REG 0x1240,

BIT 0

= 1?

REG 0x3100,

BIT 5

= 1?

REG 0x3020,

BIT 4

= 1?

REG 0x3201,

BIT 0

= 1?

REG 0x1243,

BIT 0

= 0?

REG 0x1243,

BIT 1

= 0?

REG 0x3100,

BIT 3

REG 0x1241,

BITS[4:0]

= 1?

SYSTEM CLOCK

STABLE?

VALID

INVALID

APLL0

CALIBRATED?

APLL0

LOCKED?

REFA, REFAA,

REFB, REFBB,

Aux REF0, REF1,

REF2, REF3

OR IUTS0/IUTS1?

0 TO 3,6,7,

11 TO 14?

REG 0x1241,

BITS[4:0]

REG 0x1241,

BITS[4:0]

8 OR 9?

AUX NCO

0 OR 1?

DPLL1

FEEDBACK?

= 5?

DPLL1

FREERUN?

DPLL1

HOLDOVER?

APLL1

CALIBRATED?

APLL1

LOCKED?

YES

AUX REF1

VALID?

YES

REFERENCE SOURCE VALIDATION

EXAMPLE

YES

TRANSLATION

PROFILE 0.2

BUILDOUT

EXAMPLE

YES

TRANSLATION PROFILE

0.2 HITLESS

EXAMPLE

YES

TRANSLATION PROFILE 0.2

EXTERNAL ZERO DELAY

EXAMPLE

TRANSLATION PROFILE 0.2

INTERNAL ZERO DELAY

EXAMPLE

ENTER

EXIT

0.2

DISTRIBUTION

FEEDBACK PATH

SYNCED (OR SYNC REQUEST

AWAITING TRIGGER)?

DISTRIBUTION

FEEDBACK CHANNEL NOT

POWERED DOWN?

YES

EXTERNAL

ZERO DELAY

REFERENCE SOURCE

VALID?

NOTES

1. A RANGE OF ADDRESSES OR BITS USES A COLON SEPARATOR

2. REGISTER ADDRESSES ARE SPECIFIC TO DPLL0, TRANSLATION PROFILE 0.2 (EXAMPLE), AND AUXILIARY REF1 (EXAMPLE)

REG 0x3201,

BIT 1

= 1?

REG 0x3200,

BIT 5

= 1?

REG 0x3200,

BIT 3

= 1?

YES

Figure 104. Flowchart for Translation Profile Validation

AD9546/PCBZ Datasheet(PDF) 152 Page - Analog Devices

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