AD9546SLASHPCBZ datasheet(186/205 Pages) AD

186 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 186 of 205

EEPROM USAGE

EEPROM OVERVIEW

The AD9546 supports an external, I2C-compatible, EEPROM

with dedicated access. With some restrictions, the AD9546 also

supports multidevice access to a single external EEPROM on a

shared I2C common bus. The AD9546 has an on-chip I2C

master to interface to the EEPROM through the Mx pins.

Because the default register settings of the AD9546 do not

define a specific frequency translation, the user must factory

program the EEPROM content before it can be downloaded to

the register map (either automatically or manually). If desired,

the user can store custom device configurations by manually

forcing an upload to the EEPROM via the register map.

EEPROM CONTROLLER GENERAL OPERATION

EEPROM Controller

The EEPROM controller governs all aspects of communication

with the EEPROM. Because the I2C interface uses a 100 kHz

(normal mode) or 400 kHz (fast mode) communication link,

the controller runs synchronous to an on-chip generated clock

source suitable for use as the I2C serial clock. The on-chip oscillator

enables asynchronously, immediately on a request for

activation of the controller. Upon startup, the oscillator notifies

the controller of its availability, and the controller activates.

After the requested controller operation is complete, the

controller disables the clock generator and returns to an idle

state.

EEPROM Download

An EEPROM download transfers contents from the EEPROM

to the AD9546 programming registers and invokes specific

actions per the instructions stored in the EEPROM (see Table 109).

Automatic downloading is the most common method for

initiating an EEPROM download sequence, which initiates at

power-up of the AD9546, provided Pin M3 is Logic 1 at

power-up (see the Multifunction Pins at Reset or Power-Up

section). Alternatively, instead of cycling power to the AD9546 to

initiate an EEPROM download, the user can force the RESETB

pin to Logic 0, force Pin M3 to Logic 1, then return the

RESETB pin to Logic 1, and remove the drive source from

Pin M3.

The user can also request an EEPROM download on demand

(that is, without resetting or cycling power to the AD9546) by

writing a Logic 1 to Bit 0 of Register 0x2E03.

Bit 0 does not require an IO update. Writing a Logic 1 to this

bit immediately triggers a download sequence.

The EEPROM controller sets Bit 1 of Register 0x3000 to Logic 1

while the download sequence is in progress as an indication to

the user that the controller is busy.

EEPROM Upload

To store the AD9546 register contents in the EEPROM, the

user must write a Logic 1 to Bit 0 of Register 0x2E02. Bit 0 does

not require an IO update. Writing a Logic 1 to this bit

immediately triggers an upload sequence.

The AD9546 has the equivalent of a write protect feature in that

the user must write a Logic 1 to Bit 0 of Register 0x2E00 prior to

requesting an upload to the EEPROM. Attempting to upload to

the EEPROM without first setting Bit 0 results in a fault

indication (that is, the AD9546 asserts Bit 1 of Register 0x300B).

A prerequisite to an EEPROM upload is the existence of an upload

sequence stored in the 15-byte EEPROM sequence section of

the register map (Register 0x2E10 to Register 0x2E1E). That is,

the user must store a series of upload instructions (see the

EEPROM Instruction Set section) in the EEPROM sequence

section of the register map prior to executing an EEPROM

upload.

The EEPROM controller performs an upload sequence by reading

the instructions stored in the EEPROM sequence section of the

the data stored in the EEPROM sequence section of the register

map are instructions to the EEPROM controller on what to

store in the EEPROM (including operational commands and

AD9546 register data).

The EEPROM controller sets Bit 0 of Register 0x3000 to Logic 1

while the upload sequence is in progress as an indication to the

user that the controller is busy.

Because the EEPROM sequence section of the register map is

only 15 bytes, the sequence typically cannot hold enough

instructions to upload a complete set of AD9546 data to the

EEPROM. Therefore, most upload sequences necessitate that the

user upload a series of subsequences. For example, to

accomplish a required upload sequence consisting of 20 bytes

of instructions, perform the following procedure:

1. Write the first 14 instructions to the EEPROM sequence

registers with the 15th instruction being a pause instruction

(see Table 109).

2. Initiate an EEPROM upload by writing Logic 1 to Bit 0 of

the pause instruction, it suspends the upload process and

waits for another assertion of Bit 0 of Register 0x2E02.

3. While the controller pauses, write the remaining six bytes

of the upload sequence into the EEPROM sequence

registers, followed by an end of data instruction (see

Table 109).

4. Initiate an EEPROM upload by writing Logic 1 to Bit 0 of

end of data instruction, the upload process terminates.

AD9546/PCBZ Datasheet(PDF) 186 Page - Analog Devices

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