AD9546SLASHPCBZ datasheet(187/205 Pages) AD

187 / 205 page

Data Sheet

AD9546

Rev. 0 | Page 187 of 205

The preceding procedure is an example of an upload sequence

consisting of two subsequences. Most upload sequences require

more than two subsequences. However, the procedure is the

same. Specifically, partition a long sequence into several

subsequences by using the pause instruction at the end of each

subsequence and the end of data instruction at the end of the

final subsequence.

EEPROM Checksum

When the EEPROM controller encounters an end of data

instruction (see Table 109) during an upload sequence, it

computes a 32-bit cyclic redundancy check (CRC) checksum

and appends it to the stored data in the EEPROM. Similarly,

when the EEPROM controller executes a download sequence, it

computes a checksum on-the-fly. At the end of a download

sequence, the EEPROM controller compares the newly

computed checksum to the one stored in the EEPROM. If the

two checksums do not match, the EEPROM controller asserts

Bit 3 of Register 0x3000.

To minimize the possibility of downloading a corrupted

EEPROM data set, the user can execute a checksum test by

asserting the Bit 2 of Register 0x2E00, which causes the

EEPROM controller to execute a download sequence, but without

transferring data to the AD9546 registers. The controller still

computes an on-the-fly checksum, performs the checksum

comparison, and asserts Bit 3 of Register 0x3000 if the

checksums do not match. Therefore, after the device completes

the download sequence and deasserts Bit 1 of Register 0x3000, the

user can check that Bit 3 of Register 0x3000 = 0 to verify that the

test passed. However, even if the test fails, device operation is

unaffected because there was no transfer of data to the AD9546

registers.

EEPROM Header

The EEPROM controller adds a header to stored data that

carries information related to the AD9546, such as

•

Vendor ID

•

Chip type

•

Product ID

•

Chip revision

At the beginning of an EEPROM download sequence, the

EEPROM controller compares the stored header values to the

values in the corresponding registers of the AD9546. If the

controller detects a mismatch, it asserts Bit 2 of Register 0x3000

and terminates the download.

EEPROM INSTRUCTION SET

The EEPROM controller relies on a combination of

instructions and data. An instruction consists of a single byte

(eight bits). Some instructions require subsequent bytes of

payload data. That is, some instructions are self contained

operations, whereas others are directions on how to process

subsequent payload data. Table 109 shows a summary of the

EEPROM controller instructions.

When the controller downloads the EEPROM contents to the

AD9546 registers, it does so in a linear fashion, stepping

through the instructions stored in the EEPROM. However, when

the controller uploads to the EEPROM, the sequence is a nonlinear

combination of various parts of the register map and computed

data that the controller calculates on the fly.

Table 109. EEPROM Controller Instruction Set Summary

Instruction Code (Hexadecimal)

Response

Comments

0x00 to 0x7F

Requires a 2-byte register address suffix

0x80

IO update

Assert an IO update during download

0x81 to 0x8F

Not applicable

Undefined

0x90

Calibrate all PLLs

Calibrate the system clock PLL, APLL0, and APLL1 during download

0x91

Calibrate the system clock PLL

Calibrate only the system clock PLL during download

0x92

Calibrate APLL0 and APLL1

Calibrate only APLL0 and APLL1 during download

0x93

Calibrate APLL0

Calibrate only APLL0 during download

0x94

Calibrate APLL1

Calibrate only APLL1 during download

0x95 to 0x97

Not applicable

Reserved/unused

0x98

Force freerun

Force DPLL0 and DPLL1 to freerun during download

0x99

Force DPLL0 freerun

Force only DPLL0 to freerun during download

0x9A

Force DPLL1 freerun

Force only DPLL1 to freerun during download

0x9B to 0x9F

Not applicable

Reserved/unused

0xA0

Synchronize outputs

Synchronize all distribution outputs during download

0xA1

Synchronize Channel 0

Synchronize only Channel 0 distribution outputs during download

0xA2

Synchronize Channel 1

Synchronize only Channel 1 distribution outputs during download

0xA3 to 0xAF

Not applicable

Reserved/unused

0xB0

Clear condition

Apply Condition 0 and reset the condition map

0xB1 to 0xBF

Set condition

Apply Condition 1 to Condition 15, respectively

0xC0 to 0xFD

Not applicable

Undefined

0xFE

Pause

Pause the EEPROM upload sequence

0xFF

End of data

Marks the end of the instruction sequence

AD9546/PCBZ Datasheet(PDF) 187 Page - Analog Devices

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