AD9546SLASHPCBZ datasheet(183/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 183 of 205

INTERRUPT REQUEST (IRQ)

IRQ OVERVIEW

The AD9546 monitors certain internal device events, potentially

allowing them to trigger an IRQ event. Three groups of

registers (see Figure 123) control the IRQ functionality within the

AD9546.

•

IRQ status registers (Register 0x300B through

•

IRQ mask registers (Register 0x010C through

•

IRQ clear registers (Register 0x2006 through Register 0x2019)

The IRQ logic can indicate an IRQ event status result for any

specific device events via the logical OR of the status of all the

IRQ status bits. In addition, the IRQ logic offers IRQ event

status results for select groups of specific IRQ events, namely,

the PLL0 IRQs, PLL1 IRQs, and common IRQs (see Figure 123).

The PLL0 IRQ group includes all device events associated with

DPLL0 and APLL0. The PLL1 IRQ group includes all device

events associated with DPLL1 and APLL1. The common IRQ

group includes events not associated with PLL0 or PLL1 (like

the system clock, EEPROM, reference monitors, and others).

IRQ STATUS BITS

The IRQ status bits maintain a record of specific IRQ events.

The occurrence of a specific device event results in the setting

and latching of the corresponding bit in the IRQ status registers

(assuming the user enables those specific IRQ events (see the

IRQ Mask Bits section)).

IRQ MASK BITS

The IRQ mask bits comprise a bit for bit correspondence with

the IRQ status. Writing a Logic 1 to a mask bit allows

(unmasks) the corresponding specific device event to propagate

to the IRQ status bits. A Logic 0 (default) prevents (masks) the

corresponding specific device event to propagate to the IRQ

status bits.

The presence of the IRQ mask allows the user to select certain

device events for generating an IRQ event, while ignoring

(masking) all other specific device events from contributing to

an IRQ (PLL0 IRQ, PLL1 IRQ, common IRQ, or any IRQ signal in

Figure 123).

The default state of the IRQ mask bits is Logic 0. Therefore, the

device is not capable of generating an IRQ until the user

populates the IRQ mask with a Logic 1 to unmask the desired

IRQ events. Writing a Logic 1 to an IRQ mask bit may result in

immediate indication of an IRQ if the corresponding IRQ event

is already asserted (that is, the device previously registered the

corresponding IRQ event).

IRQ CLEAR BITS

The IRQ clear bits comprise a bit for bit correspondence with

the IRQ status bits. Writing a Logic 1 to an IRQ clear bit forces

the corresponding IRQ event to Logic 0, thereby clearing that

specific IRQ event. The IRQ clear registers are autoclearing.

Therefore, after writing a Logic 1 to any IRQ clear bit in

restores the IRQ clear bit to Logic 0. The IRQ remains asserted

until the user clears all of the IRQ clear bits associated with

PLL0 IRQ, PLL1 IRQ, common IRQ, or any IRQ signal shown

in Figure 123).

Although it is not recommended, in certain applications, it

may be desirable to clear an entire IRQ group all at one time.

0 clears all IRQ clear bits. Bit 1 clears the IRQ clear bits

associated with the common IRQ bits. Bit 2 clears the IRQ clear

bits associated with the PLL0 IRQ bits. Bit 3 clears the IRQ

clear bits associated with the PLL1 IRQ bits.

Alternatively, the user can program any of the multifunction

pins as an input for clearing an IRQ group, which allows

clearing an IRQ group with an external logic signal rather than

by writing to Register 0x2005 (see Figure 123).

The recommendation for clearing IRQ events is to first service

the specific IRQ event (as needed) and then clear the specific

IRQ for the given IRQ event. Clearing IRQ groups via

an IRQ group all at one time may result in the unintentional

clearing of one or more asserted IRQ events. Clearing asserted

IRQ events eliminates the record of the associated device

events, subsequently erasing any history of those events having

occurred.

AD9546/PCBZ Datasheet(PDF) 183 Page - Analog Devices

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