9.3.2.2 Powered-Off Protection

source (Sx) pins of the device remain in high impedance (Hi-Z) state, and the device performance remains within

the leakage performance. Powered-off protection minimizes system complexity by removing the need to control

power supply sequencing of the system. The feature prevents errant voltages on the input source pins from

reaching the rest of the system and maintains isolation when the system is powering up. Without powered-off

protection, signal on the input source pins can back-power the supply rails through internal ESD diodes and

cause potential damage to the system.

must always be present to ensure proper operation. Source and drain voltage levels of up to ±60 V are blocked

in the powered-off condition.

9.3.2.3 Fail-Safe Logic

Fail-safe logic circuitry allows voltages on the digital control pins to be applied before the supply pins, protecting

the device from potential damage. The switch is specified to be in the OFF state, regardless of the state of the

digital logic signals. The digital inputs are protected against positive faults of up to +44 V in powered-off

condition, but do not offer protection against negative overvoltage condition.

9.3.2.4 Overvoltage Protection and Detection

The TMUX7411F, TMUX7412F, and TMUX7413F detect overvoltage inputs by comparing the voltage on a

The switch automatically turns OFF regardless of the logic controls when an overvoltage is detected. The source

pin becomes high impedance and ensures only small leakage current flows through the switch. The drain pin

(Dx) is pulled to the supply that was exceeded when the fault channel is selected by the logic control. For

current is limited to roughly 1 mA during a shorted load (to GND) condition.

9.3.2.5 Latch-up Immunity

Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition

is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains

even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic

damage due to excessive current levels. The Latch-up condition typically requires a power cycle to eliminate the

low impedance path.

In the TMUX7411F, TMUX7412F, and TMUX7413F devices, an insulating oxide layer is placed on top of the

silicon substrate to prevent any parasitic junctions from forming. As a result, the devices are latch-up immune

under all circumstances by device construction.

9.3.3 Overvoltage Fault Flags

The voltages on the source input pins of the TMUX7411F, TMUX7412F, and TMUX7413F are continuously

monitored, and the status of whether an overvoltage condition occurs is indicated by an active low general fault

flag (FF). The voltage on the FF pin indicates if any of the source input pins are experiencing an overvoltage

The FF pin is an open-drain output and an external pull-up resistor of 1 kΩ is recommended. The pull-up voltage

can be in the range of 1.8 V to 5.5 V, depending on the controller voltage the device interfaces with.

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TMUX7411F, TMUX7412F, TMUX7413F

SCDS404 – MARCH 2021

Copyright © 2021 Texas Instruments Incorporated

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Product Folder Links: TMUX7411F TMUX7412F TMUX7413F