 |
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
|
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
LP87702 Datasheet(PDF) 32 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
LP87702 Datasheet(HTML) 32 Page - Texas Instruments |
|
|
32 / 98 page  PG1 CONTROL Mask Falling Status INT Mask Rising PG0 PG1/GPO1 Mask Status INT Mask Falling Status INT Mask Rising Mask Falling Status INT Mask Rising Mask Falling Status INT Mask Rising Mask Falling Status INT Mask Rising Mask Falling Status INT Mask Rising nINT Boost Powergood Buck0 Powergood Buck1 Powergood VANA Powergood Thermal Warn VMON1 Powergood VMON2 Powergood SEL_PG0_VMON1 SEL_PG0_VANA SEL_PG0_BUCK1 SEL_PG0_BUCK0 SEL_PG0_BOOST SEL_PG0_VMON2 GPO1 VANA VMON1 VMON2 PP/OD Polarity PP/OD EN_PGOOD_BOOST EN_PGOOD_BUCK0 EN_PGOOD_BUCK1 EN_PGOOD_VANA EN_PGOOD_VMON1 EN_PGOOD_VMON2 GPO1_SEL SEL_PG0_TWARN PG0 CONTROL Figure 7-9. Block Diagram of Power-Good Connections LP87702 power-good detection has two operating modes selected in the OTP: gated (that is, unusual) or continuous (that is, invalid) mode of operation. These modes are described in Section 7.3.10.3.1 and in Section 7.3.10.3.2. 7.3.10.3.1 PGx Pin Gated (Unusual) Mode The PGx signal detects unexpected or unusual situations in this mode. Mode is selected by setting the PGx_MODE bit to 0 in the PG_CTRL register. For the gated mode of operation, the PGx behaves as follows: • PGx is set to active or asserted state upon exiting the OTP configuration as an initial default state. • The PGx status is active or asserted during an 800-μs gated time period from the enable activation for each enabled rail, thereby gating-off the status indication. • The PGx state typically remains active or asserted for normal conditions during normal power-up sequencing and requested voltage changes. • The PGx status could change to inactive or de-asserted after an 800-μs gated time period if any output voltage is outside of regulation range during an abnormal power-up sequencing and requested voltage changes. • Using the gated mode of operation could allow the PGx signal to initiate an immediate power shutdown sequence if the PGx signal is wired-OR with signal connected to the EN input. This type of circuit configuration provides a smart PORz function for processor that eliminates the need for additional components to generate PORz upon start-up and to monitor voltage levels of key voltage domains. PGx signal is set inactive if the output voltage of a monitored buck or boost converter is invalid or the output voltage is not valid at 800 µs from the enable of the converter, which should be considered when selecting the BUCKx_SLEW_RATE setting. Keep the sum of the soft start time and slew rate controlled part of the voltage LP87702 SNVSBU3 – MARCH 2021 www.ti.com 32 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP87702 |
|
Enlace URL |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Enlace a la hoja de datos | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Mexican ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
