LP87702 datasheet(29/98 Pages) TI

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enabled monitorings. Section 7.3.10.3describes how the enabled monitoring signals are combined to generate

power-good (PG0 and PG1) and interrupts. Monitoring comparators have a dedicated reference and bias block,

which is independent of the main reference and bias block.

Nominal level for the output voltage of BUCKx converter is set with BUCKx_VSET in the BUCKx_VOUT

BUCKx_WINDOW as ± 30 mV, ± 50 mV, ± 70 mV or ± 90 mV. Nominal level for the output voltage of the

BOOST converter is set with BOOST_VSET in the BOOST_CTRL register. Available levels are 4.9 V, 5 V,

5.1 V, and 5.2 V. Overvoltage and undervoltage detection levels, with respect to nominal level, are selected

with BOOST_WINDOW as ± 2%, ± 4%, ± 6% or ± 8%. Converter monitoring window selection bits are in the

PGOOD_LEVEL_3 register.

Input voltage of LP87702 is monitored at the VANA pin. Nominal level can be selected as 3.3 V or 5 V with the

VANA_THRESHOLD bit. Overvoltage and undervoltage detection levels are selected with VANA_WINDOW as

(nominal). VANA_THRESHOLD and VANA_WINDOW are set in the PGOOD_LEVEL_2 register.

VMON1 and VMON2 inputs can be used for monitoring external rails in the system. VMONx settings are

defined in the PGOOD_LEVEL_1 and PGOOD_LEVEL_2 registers. Nominal value for the input level of VMONx

is selected with VMONx_THRESHOLD, between 0.65 V to 1.8 V. Higher voltage levels or levels not directly

supported can be monitored using an external resistor divider. In this case VMONx_THRESHOLD must be set

as 0.65 V to have a high-impedance input, and the resistor divider must scale the monitored level down to 0.65 V

at the VMONx pin. Overvoltage and undervoltage detection levels are selected with VMONx_WINDOW as ± 2%,

± 3%, ± 4% or ± 6%.

See Section 6 for more details on the accuracy of the monitoring windows and deglitch filtering.

7.3.10.2 Interrupts

The LP87702 sets the flag bits indicating what protection or warning conditions have occurred, and the nINT pin

is pulled low. The nINT output pin is driven high after all the flag bits and pending interrupts are cleared.

Fault detection is indicated by the RESET_REG_INT interrupt flag bit set in the INT_TOP_2 register after the

start-up event.

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LP87702

SNVSBU3 – MARCH 2021

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LP87702 Datasheet(PDF) 29 Page - Texas Instruments