Product Specification

PE9601

Page 7 of 14

Document No. 70-0025-05

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©2005 Peregrine Semiconductor Corp. All rights reserved.

Table 6. AC Characteristics

Symbol

Parameter

Test Program Name

Conditions

Min

Max

Units

Control Interface and Latches (see Figure 5 and Figure 6)

Serial data clock frequency

(Note 1)

10

MHz

Serial clock HIGH time

t_clk_H (s)

30

ns

Serial clock LOW time

t_clk_L (s)

30

ns

Sdata set-up time after Sclk rising

edge, D[7:0] set-up time to

M1_WR, M2_WR, A_WR, E_WR

rising edge

t_dsu_”xxx” (s) where

“xxx” is name of pin being

tested

10

ns

Sdata hold time after Sclk rising

edge, D[7:0] hold time to M1_WR,

M2_WR, A_WR rising edge

t_dhid_”xxx” (s) where

“xxx” is name of pin being

tested

10

ns

S_WR, M1_WR, M2_WR, A_WR,

E_WR pulse width

t_pw_”xxx” (s) where “xxx”

is name of pin being

tested

30

ns

Sclk rising edge to S_WR rising

edge. S_WR, M1_WR, M2_WR,

A_WR falling edge to Hop_WR

rising edge

t_cwr_”xxx” (s) where

“xxx” is name of pin being

tested

30

ns

Sclk falling edge to E_WR

transition

t_ce (s)

30

ns

S_WR falling edge to Sclk rising

edge. Hop_WR falling edge to

S_WR, M1_WR, M2_WR, A_WR

rising edge

t_wrc_”xxx” (s) where

“xxx” is name of pin being

tested

30

ns

E_WR transition to Sclk rising

edge

t_ec (s)

30

ns

Main Divider (Including Prescaler)

Operating frequency

RF_sens

200

2200

MHz

Input level range

RF_sens

External AC coupling

0

5

dBm

Main Divider (Prescaler Bypassed)

Operating frequency

20

220

MHz

Input level range

External AC coupling

-5

5

dBm

Reference Divider

Operating frequency

Fc_sens

(Note 3)

100

MHz

Reference input power (Note 2)

Fc_sens

Single ended input

-2

dBm

Phase Detector

Comparison frequency

(Note 3)

20

MHz

Note 1:

Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk

specification.

Note 2:

Note 3:

Parameter is guaranteed through characterization only and is not tested.