Product Specification

PE9601

Page 10 of 14

©2005 Peregrine Semiconductor Corp. All rights reserved.

Document No. 70-0025-05

│ UltraCMOS™ RFIC Solutions

The double buffering provided by the primary and

secondary registers allows for “ping-pong” counter

control using the FSELS input. When FSELS is

“high”, the primary register contents set the

counter inputs. When FSELS is “low”, the

secondary register contents are utilized.

While the E_WR input is “high” and the S_WR

The enhancement register is double buffered to

prevent inadvertent control changes during serial

loading, with buffer capture of the serially entered

data performed on the falling edge of E_WR

according to the timing diagram shown in Figure

7. After the falling edge of E_WR, the data

provide control bits as shown in Table 8 with bit

functionality enabled by asserting the Enh input

“low”.

Table 7. Primary Register Programming

Interface

Mode

Enh

Bmode

Smode

Pre_en

Parallel

1

0

0

M2_WR rising edge load

M1_WR rising edge load

A_WR rising edge load

Serial*

1

0

1

Direct

1

1

X

0

0

0

0

Pre_en

*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.

Table 8. Enhancement Register Programming

Interface

Mode

Enh

Bmode

Smode

Reserved

Reserved

Reserved

Power

down

Counter

load

MSEL

output

Prescaler

output

Parallel

0

X

0

E_WR rising edge load

Serial*

0

X

1

*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.

MSB (first in)

MSB (first in)

(last in) LSB

(last in) LSB