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MIC2133 Datasheet(PDF) 34 Page - Microchip Technology

No. de pieza MIC2133
Descripción Electrónicos  75V Dual Phase, Advanced COT Buck Controller with Selectable Droop Feature and Phase Shedding
PDF  50 Pages
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Fabricante Electrónico  MICROCHIP [Microchip Technology]
Página de inicio  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MIC2133 Datasheet(HTML) 34 Page - Microchip Technology

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 2022 Microchip Technology Inc. and its subsidiaries
DS20006653B-page 34
MIC2133
The maximum value of the overall ESR of the output
capacitor in steady state is calculated in the equation
below.
EQUATION 5-12:
The maximum overall ESR value of the output
capacitor must also meet the load transient
requirement and is calculated in the equation below.
Then, the lower value must be chosen for the output
capacitor ESR.
EQUATION 5-13:
As described in Section 4.1 “Control Architecture”,
the MIC2133 requires at least 20 mV peak-to-peak rip-
ple at the FBS pin to make the gm amplifier and the error
comparator behave properly.
Also, it is recommended that the output voltage ripple
be in phase with the inductor current.
Therefore, it is recommended that the output voltage
ripple caused by the output capacitor’s value be much
smaller than the ripple caused by the output capacitor’s
ESR. If low-ESR capacitors, such as ceramic capaci-
tors, are selected as the output capacitors, a ripple
injection method must be applied to provide enough
feedback voltage ripple. Refer to Section 4.4 “Ripple
Injection Circuit Components Selection” for more
details.
It is recommended that the voltage rating of the output
capacitor be 25% greater than the maximum output
voltage. The output capacitor RMS current is calcu-
lated in the equation below.
EQUATION 5-14:
The power dissipated in the output capacitor is
calculated in the equation below.
EQUATION 5-15:
5.3
Input Capacitor Selection
In addition to high-frequency ceramic capacitors, it is
recommended that a larger bulk capacitance, either
ceramic or aluminum electrolytic, be used to help
attenuate ripple on the input and to supply current to
the input during large output current transients. It is
recommended that the input capacitor for the power
stage input, VIN, be selected for the ripple voltage at
VIN, capacitance, ESR, ripple current rating and
voltage rating. Tantalum input capacitors may fail when
subjected to high inrush currents caused by turning the
input supply on. A tantalum input capacitor’s voltage
rating must be at least two times the maximum input
voltage to maximize reliability. Aluminum electrolytic,
OS-CON and multilayer polymer film capacitors can
handle the higher inrush currents without voltage
derating. Due to the ripple cancellation effect of the
two-phase buck converter, the input ripple voltage and
ripple current are smaller than those of the
single-phase converter, and the effective ripple
frequency seen by the input capacitor is twice the
switching frequency. The input ripple voltage depends
on the IOUT and input capacitor’s capacitance and
ESR. The steady state input voltage ripple can be
estimated by the equation below.
EQUATION 5-16:
The capacitance of the input capacitor can be
determined in the equation below.
EQUATION 5-17:
The ESR of the total input capacitance can be
determined in the equation below.
EQUATION 5-18:
The input capacitor must be rated for the input current
ripple. The rated RMS value of the input capacitor cur-
rent is determined at the maximum output current.
ESRCOUT
V
OUT PP

I
OPP
----------------------------
ESRCOUT
V
OUT TRANS

I
LOAD
-------------------------------------
ICOUT RMS

I
OPP
12
----------------
=
PDISS COUT

ICOUT RMS

2
ESR
COUT
=
Where:
IOUT = Total Output Current
D = Duty Cycle per Phase
n = Total Number of Phases
k = 0,1 for D > k/n and k < n
fSW
Switching Frequency per Phase
CIN = Total Input Capacitance
ESRCIN = Equivalent Series Resistance of Input
Capacitor
CIN
IOUT D
k
n
---


1
n
---
D
k
n
---


n fSW
V
IN
--------------------------------------------------------------------------------
Where:
k = 0,1 for D > k/n and k < n
n = Total Number of Phases
ESRCIN VIN
n
IOUT
------------
VIN ≈
k
n
n × fSW × CIN
IOUT × D –×
1
n
[]
– D –
k
n
× ESRCIN
IOUT
n
+



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