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M95128-DF Datasheet(PDF) 13 Page - STMicroelectronics

No. de pieza M95128-DF
Descripción Electrónicos  128-Kbit serial SPI bus EEPROM with high-speed clock
PDF  48 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M95128-DF Datasheet(HTML) 13 Page - STMicroelectronics

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6.2
Write disable (WRDI)
One way of resetting the Write enable latch (WEL) bit is to send a Write disable instruction to the device.
As shown in Figure 9, to send this instruction to the device, Chip select (S) is driven low, and the bits of the
instruction byte are shifted in, on Serial data input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip select (S) being driven
high.
The Write enable latch (WEL) bit, in fact, becomes reset by any of the following events:
•
Power-up
•
WRDI instruction execution
•
WRSR instruction completion
•
WRITE instruction completion.
Figure 9. Write disable (WRDI) sequence
C
D
Q
2
1
3
4
5
6
7
High Impedance
0
Instruction
S
M95128-W M95128-R M95128-DF
Write disable (WRDI)
DS1356 - Rev 20
page 13/48



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