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STM32H7B3AI Datasheet(PDF) 134 Page - STMicroelectronics

No. de pieza STM32H7B3AI
Descripción Electrónicos  32-bit Arm® Cortex®-M7 280 MHz MCUs, 2-Mbyte flash memory, 1.4-Mbyte RAM, 46 com. and analog interfaces, SMPS, crypto
PDF  238 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32H7B3AI Datasheet(HTML) 134 Page - STMicroelectronics

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Symbol
Parameter
Min(1)
Max(1)(2)
Unit
th(CLKH-NWAIT)
ns
FMC_NWAIT valid after FMC_CLK high
1
-
1. Guaranteed by characterization results.
2. At VOS1, these values are degraded by up to 5 %.
Figure 42. Synchronous non-multiplexed PSRAM write timings
FMC_CLK
FMC_NEx
FMC_A[25:0]
FMC_NWE
FMC_D[15:0]
D1
D2
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tw(CLK)
tw(CLK)
Data latency = 0
td(CLKL-NExL)
td(CLKH-NExH)
td(CLKL-AV)
td(CLKH-AIV)
td(CLKH-NWEH)
td(CLKL-NWEL)
td(CLKL-Data)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
FMC_NADV
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-Data)
FMC_NBL
td(CLKH-NBLH)
Table 83. Synchronous non-multiplexed PSRAM write timings
Symbol
Parameter
Min(1)
Max(1)(2)
Unit
t(CLK)
FMC_CLK period
2Tfmc_ker_ck − 0.5
-
ns
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2)
-
2
t(CLKH-NExH)
FMC_CLK high to FMC_NEx high (x= 0…2)
Tfmc_ker_ck + 1.5
-
td(CLKL-NADVL)
FMC_CLK low to FMC_NADV low
-
1.5
td(CLKL-NADVH)
FMC_CLK low to FMC_NADV high
0
-
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x=16…25)
-
2
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid (x=16…25)
Tfmc_ker_ck + 1.5
-
td(CLKL-NWEL)
FMC_CLK low to FMC_NWE low
-
1.5
td(CLKH-NWEH)
FMC_CLK high to FMC_NWE high
Tfmc_ker_ck + 1
-
STM32H7B3xI
Operating conditions
DS13139 - Rev 8
page 134/238



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