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STM32H7B3AI Datasheet(PDF) 19 Page - STMicroelectronics |
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STM32H7B3AI Datasheet(HTML) 19 Page - STMicroelectronics |
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19 / 238 page  3.9 Bus-interconnect matrix The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow interconnecting bus masters with bus slaves (see Figure 3. STM32H7B3xI bus matrix). Figure 3. STM32H7B3xI bus matrix APB1 SDMMC1 MDMA DMA2D LTDC APB4 Cortex-M7 I$ 16KB D$ 16KB APB3 32-bit AHB bus matrix CD domain 64-bit AXI bus matrix CD domain 32-bit AHB bus matrix SRD domain DTCM 128 Kbytes ITCM 64 Kbytes Flash Bank 1 1 Mbyte Flash Bank 2 1 Mbyte FMC AHB SRAM1 64 Kbytes AHB1 AHB2 AHB4 SRD SRAM 32 Kbytes Backup SRAM 4 Kbytes AHBS CPU AXI to AHB CD-to-SRD AHB 32-bit bus 64-bit bus Bus multiplexer Legend Master interface Slave interface AHB3 AXI AHB APB APB2 TCM AXI SRAM3 384 Kbytes AXI SRAM2 384 Kbytes AXI SRAM1 256 Kbytes OTFDEC1 OCTOSPI1 FLIFT GFX-MMU DMA2 SDMMC2 DMA1 USBHS1 BDMA1 AHB SRAM2 64 Kbytes BDMA2 OTFDEC2 OCTOSPI2 |
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