STM32H7B3AI datasheet(25/238 Pages) STMICROELECTRONICS

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“Regular” or “injected” conversions:

–

“regular” conversions can be requested at any time or even in continuous mode without having any

impact on the timing of “injected” conversions

–

“injected” conversions for precise timing and with high conversion priority

3.27

Digital camera interface (DCMI)

The devices embed a camera interface that can connect with camera modules and CMOS sensors through an

8-bit to 14-bit parallel interface, to receive video data. The camera interface can achieve a data transfer rate up to

140 Mbyte/s using a 80 MHz pixel clock. It features:

•

Programmable polarity for the input pixel clock and synchronization signals

•

Parallel data communication can be 8-, 10-, 12- or 14-bit

•

Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB

565 progressive video or compressed data (like JPEG)

•

Supports continuous mode or snapshot (a single frame) mode

•

Capability to automatically crop the image

3.28

Parallel synchronous slave interface (PSSI)

The PSSI is a generic synchronous 8-/16-bit parallel data input/output slave interface. It allows the transmitter

to send a data valid signal to indicate when the data is valid, and the receiver to output a flow control signal to

indicate when it is ready to sample the data.

The PSSI main features are:

•

Slave mode operation

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8- or 16-bit parallel data input or output

•

8-word (32-byte) FIFO

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Data enable (DE) alternate function input and Ready (RDY) alternate function output.

When enabled, these signals can either allow the transmitter to indicate when the data is valid or the receiver to

indicate when it is ready to sample the data, or both.

The PSSI shares most of the circuitry with the digital camera interface (DCMI). It thus cannot be used

simultaneously with the DCMI.

3.29

LCD-TFT display controller (LTDC)

The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals

to interface directly to a broad range of LCD and TFT panels up to XGA (1024x768) resolution with the following

features:

•

2 display layers with dedicated FIFO (64x32-bit)

•

Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer

•

Up to 8 input color formats selectable per layer

•

Flexible blending between two layers using alpha value (per pixel or constant)

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Flexible programmable parameters for each layer

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Color keying (transparency color)

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Up to 4 programmable interrupt events

•

AXI master interface with burst of 16 words

3.30

JPEG codec (JPEG)

The JPEG codec can encode and decode a JPEG stream as defined in the

ISO/IEC10918-1 specification. It provides an fast and simple hardware compressor and decompressor of JPEG

images with full management of JPEG headers.

The JPEG codec main features are as follows:

•

8-bit/channel pixel depths

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Single clock per pixel encoding and decoding

•

Support for JPEG header generation and parsing

STM32H7B3xI

Digital camera interface (DCMI)

DS13139 - Rev 8

page 25/238

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