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STM32H7B3AI Datasheet(PDF) 161 Page - STMicroelectronics

No. de pieza STM32H7B3AI
Descripción Electrónicos  32-bit Arm® Cortex®-M7 280 MHz MCUs, 2-Mbyte flash memory, 1.4-Mbyte RAM, 46 com. and analog interfaces, SMPS, crypto
PDF  238 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32H7B3AI Datasheet(HTML) 161 Page - STMicroelectronics

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Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DuCyCKOUT
Output
clock
frequency
duty cycle
1.62 < VDD < 3.6 V
Odd
division,CKOUTDIV[7:0]
= n, 2, 4, 6, ...
%
(((n/
2+1)/(n−1))*100)−5
(((n/2+1)/
(n−1))*100)
(((n/
2+1)/(n−1))*100)+5
twh(CKIN)
twl(CKIN)
Input clock
high and
low time
SPI mode
(SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
-
TCKIN/2 - 0.5
TCKIN/2
-
ns
tsu
Data input
setup time
SPI mode
(SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
-
4
-
-
th
Data input
hold time
SPI mode
(SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
-
0.5
-
-
TManchester
Manchester
data period
(recovered
clock
period)
Manchester mode
(SITP[1:0]=2,3),
Internal clock mode
(SPICKSEL[1:0]¹0),
1.62 < VDD < 3.6 V
-
(CKOUTDIV[7:0]+1)
x TDFSDMCLK
-
(2*CKOUTDIV[7:0])
x TDFSDMCLK(3)
1. The maximum DFSDM kernel clock is specified in Section 6.3.1 .
2. The internal DFSDMCLK clock must be at least 4 times faster than the external CKIN clock.
3. The internal DFSDMCLK must be at least 6 times faster than the Manchester data frequency.
STM32H7B3xI
Operating conditions
DS13139 - Rev 8
page 161/238



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