STM32H7B3AI datasheet(182/238 Pages) STMICROELECTRONICS

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Figure 79. ULPI timing diagram

Clock

Control In

(ULPI_DIR,ULPI_NXT)

data In

(8-bit)

Control out

(ULPI_STP)

data out

(8-bit)

tDD

tDC

tHD

tSD

tHC

tSC

tDC

6.3.36.10

JTAG/SWD interface characteristics

Unless otherwise specified, the parameters given in Table 126 and Table 127 for JTAG/SWD are derived from

tests performed under the ambient temperature, frcc_cpu_ck frequency and VDD supply voltage summarized in

Table 22. General operating conditions and Section 6.3.1 , with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

•

Capacitive load CL=30 pF

•

Measurement points are done at CMOS levels: 0.5VDD

•

VOS level set to VOS0

Note:

At VOS1, the performance can be degraded by up to 5 % compared to VOS0. This is indicated by a footnote

when applicable.

Refer to Section 6.3.16 I/O port characteristics for more details on the input/output characteristics:

Table 126. Dynamics JTAG characteristics

Symbol

Parameter

Conditions

Min

Typ

Max(1)

Unit

Fpp

TCK clock frequency

2.7 V <VDD< 3.6 V

MHz

1/tc(TCK)

1.62 V <VDD< 3.6 V

27.5

tisu(TMS)

TMS input setup time

tih(TMS)

TMS input hold time

tisu(TDI)

TDI input setup time

1.5

tih(TDI)

TDI input hold time

tov(TDO)

TDO output valid time

2.7 V <VDD< 3.6 V

1.62 V <VDD< 3.6 V

toh(TDO)

TDO output hold time

1. At VOS1, these values are degraded by up to 5 %.

Table 127. Dynamics SWD characteristics

Symbol

Parameter

Conditions

Min

Typ

Max(1)

Unit

Fpp

SWCLK clock frequency

2.7V <VDD< 3.6 V

MHz

1/tc(SWCLK)

1.62 <VDD< 3.6 V

55.5

STM32H7B3xI

Operating conditions

DS13139 - Rev 8

page 182/238

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