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STM32H7B3II Datasheet(PDF) 166 Page - STMicroelectronics

No. de pieza STM32H7B3II
Descripción Electrónicos  32-bit Arm® Cortex®-M7 280 MHz MCUs, 2-Mbyte flash memory, 1.4-Mbyte RAM, 46 com. and analog interfaces, SMPS, crypto
PDF  238 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32H7B3II Datasheet(HTML) 166 Page - STMicroelectronics

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6.3.33
LCD-TFT controller (LTDC) characteristics
Unless otherwise specified, the parameters given in Table 112 for LCD-TFT are derived from tests performed
under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 22. General
operating conditions and Section 6.3.1 , with the following configuration:
•
LCD_CLK polarity: high
•
LCD_DE polarity: low
•
LCD_VSYNC and LCD_HSYNC polarity: high
•
Pixel formats: 24 bits
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Capacitive load CL=30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
•
IO Compensation cell activated.
•
HSLV activated when VDD ≤ 2.7 V
•
VOS level set to VOS 0
Note:
At VOS1, the performance can be degraded by up to 5 % compared to VOS0. This is indicated by a footnote
when applicable.
Table 112. LTDC characteristics
Symbol
Parameter
Conditions
Min
Max(1)
Unit
fCLK
LTDC clock output frequency
2.7 V < VDD < 3.6 V, 20 pF
-
140
MHz
2.7 V < VDD < 3.6 V
-
133
1.62 V < VDD < 3.6 V
-
66.5
DCLK
LTDC clock output duty cycle
-
45
55
%
tw(CLKH), tw(CLKL)
Clock High time, low time
-
tw(CLK)/2−0.5
tw(CLK)/2+0.5
ns
tv(DATA)
Data output valid time
2.7 V < VDD < 3.6 V
-
3.0
1.62 V < VDD < 3.6 V
-
7.5
th(DATA)
Data output hold time
-
0
-
tv(HSYNC), tv(VSYNC), tv(DE)
HSYNC/VSYNC/DE output valid time
2.7 V < VDD < 3.6 V
-
3.0
1.62 V < VDD < 3.6 V
-
7.5
th(HSYNC), th(VSYNC), th(DE)
HSYNC/VSYNC/DE output hold time
-
0
-
1. At VOS1, these values are degraded by up to 5 %.
STM32H7B3xI
Operating conditions
DS13139 - Rev 8
page 166/238



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