CS5920 datasheet(76/160 Pages) AMCC

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S5920 – PCI Product

Revision 1.01 – November 28, 2005

AMCC Confidential and Proprietary

DS1596

Data Book

ADD-ON BUS OPERATION REGISTERS

The Add-On bus interface provides access to 8

DWORDs of data, control and status information. All of

these locations are accessed by asserting the Add-On

bus chip select pin (SELECT#) and the byte-enable

pins (BE[3:0]), in conjunction with either the read or

write control enables (signal pin RD# or WR#). All reg-

isters are accessed with signals synchronous to the

Add-On clock.

This register group represents the primary method for

communication between the Add-On and PCI buses

as viewed by the Add-On. The flexibility of this

arrangement allows a number of user-defined soft-

ware protocols to be built. One should NOT read/write

from any undefined address, or the read results and

write effects cannot be guaranteed. Table 6 lists the

Add-On Bus Operation Registers.

Table 44. Operation Registers - Add-On Interface

Address

Abbreviation

0Ch

AIMB

Add-On Incoming Mailbox Register

1Ch

AOMB

Add-On Outgoing Mailbox Register

28h

APTA

Add-On Pass-Thru Address Register

2Ch

APTD

Add-On Pass-Thru Data Register

34h

AMBEF

Add-On Mailbox Empty/Full Status Register

38h

AINT

Add-On Interrupt Control/Status Register

3Ch

ARCR

Add-On Reset Control Register

60h

APTCR

Add-On Pass-Thru Configuration Register

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