CS5920 datasheet(98/160 Pages) AMCC

98 / 160 page

S5920 – PCI Product

Revision 1.01 – November 28, 2005

AMCC Confidential and Proprietary

DS1596

Data Book

1. Memory Read Multiple and Memory Read Line are executed as a Memory Read.

2. Memory Write and Invalidate is executed as a Memory Write.

PCI BURST TRANSFERS

The PCI bus, by default, expects burst transfers to be

executed. To successfully perform a burst transfer,

both the initiator and target must order their burst

address sequence in an identical fashion. There are

two different ordering schemes: linear address incre-

menting and 80486 cache line fill sequencing.

The S5920 supports only linear burst ordering.

Attempts to perform burst transfers with a scheme

other than this will cause the STOP# signal to be

asserted during the first data phase, thus issuing a dis-

connect to the initiator. The S5920 completes the initial

data phase successfully, but asserting STOP# indi-

cates that the next access needs to be a completely

new cycle.

Some accesses to the S5920 controller do not support

burst transfers. For example, the S5920 does not

allow burst transfers when accesses are made to the

configuration or operation registers. Attempts to per-

form burst transfers to these regions will cause a

disconnect on the PCI bus, as described above.

Expansion ROM accesses also do not support bursts,

and will respond in the same way. Accesses to mem-

ory or I/O regions defined by the Base Address

Registers 1-4 may be bursts, if desired.

PCI READ TRANSFERS

The S5920 responds to PCI bus memory or I/O read

transfers when it is selected as a target.

PCI targets may drive DEVSEL# and TRDY# after the

end of the address phase. TRDY# is not driven until

the target can provide valid data for the PCI read.

Read accesses from the S5920 operation registers

are shown in Figure 1. The S5920 conditionally

asserts STOP# in clock period 3 if the initiator keeps

FRAME# asserted during clock period 2 with IRDY#

asserted (indicating a burst is being attempted). Wait

states may be added by the initiator by not asserting

the signal IRDY# during clock 3 and beyond. If

FRAME# remains asserted, but IRDY# is not

asserted, the initiator is just adding wait states, not

necessarily attempting a burst.

Figure 45. Single Data Phase PCI Bus Read of S5920

Registers or Expansion ROM

There are only two conditions where accesses to the

S5920 do not return TRDY#, but assert STOP#

instead. This condition is called a target-initiated termi-

nation or target disconnect. This can occur when a

read attempt is made to an empty Pass-Thru FIFO.

The second condition may occur when read accesses

to the expansion ROM generate a retry if the nvRAM

interface has not finished reading 4 bytes.

When burst read transfers are attempted to the S5920

operation registers, configuration registers or expan-

sion ROM, STOP# is asserted during the first data

transfer to indicate to the initiator that no further trans-

fers (data phases) are possible. This is a target-

initiated termination where the target disconnects after

the first data phase. Figure 2 shows the signal relation-

ships during a burst read attempt to the S5920

operation registers.

1101

Reserved

1110

Memory Read Line

Yes 1

1111

Memory Write and Invalidate

Yes 2

Table 52. PCI Bus Commands (Continued)

C/BE[3:0]#

Command Type

Supported

FRAME#

AD[31:0]

C/BE[3:0]#

IRDY#

TRDY#

DEVSEL#

STOP#

12345

PCLK

Address

Data

Bus Cmd

Byte Enables

(I)

(T)

(I) Driven by Initiator

(T) Driven by Target

CS5920 Datasheet(PDF) 98 Page - Applied Micro Circuits Corporation

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