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AM79C874VC Datasheet(PDF) 39 Page - Advanced Micro Devices |
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AM79C874VC Datasheet(HTML) 39 Page - Advanced Micro Devices |
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39 / 60 page ![]() Am79C874 39 P R E L I M INARY Mode Control Register (Register 21) Table 23. Mode Control Register (Register 21) Reg Bit Name Description Read/ Write Default 21 15 Reserved RO 0 21 14 Force_Link_10 1 = Force link up without checking NLP. Forced during local loopback. 0 = Normal Operation. RW 0 21 13 Force_Link_100 1 = Ignore link in 100BASE-TX and transmit data. Auto- Negotiation must be disabled at this time (pin 56 tied low). 0 = Normal Operation. RW 0 21 12 Jabber Disable 1 = Disable Jabber function in PHY. 0 = Enable Jabber function in PHY. RW 0 21 11 7_Wire_Enable 1 = Enable 7-wire interface for 10BASE-T operation. This bit is useful only when the chip is not in PCS bypass mode. 0 = Normal operation. RW 0 21 10 CONF_ALED 1 = Activity LED only responds to receive operation. 0 = Activity LED responds to receive and transmit operations for Half Duplex. LED responds to receive activity in Full Duplex operation. This bit should be ignored when Register 0.8 is set to 1 or during repeater mode operation. RW 0 21 9 LED_SEL 1 = Select NetPHY-1LP device ‘s Standard LED configuration. 0 = Use the Advanced LED configuration. RW Set by LEDRX/ LED_SEL 21 8 FEF_DISABLE 0 = Enable far-end-fault generation and detection function. 1 = Disable far-end-fault. This bit should be ignored when FX mode is disabled. RW Set by TECH[2:0], FX_SEL, ANEGA pins 21 7 Force FEF Transmit This bit is set to force to transmit Far End Fault (FEF) pattern. RW 0 21 6 RX_ER_CNT Full When Receive Error Counter is full, this bit will be set to 1. RO/ RC 0 21 5 Disable RX_ER_CNT 1 = Disable Receive Error Counter. 0 = Enable Receive Error Counter. RW 0 21 4 DIS_WDT 1 = Disable the watchdog timer in the decipher. 0 = Enable watchdog timer. RW 0 21 3 EN_RPBK 1 = Enable remote loopback (MDI loopback for 100BASE-TX). 0 = Disable remote loopback. RW 0 21 2 EN_SCRM 1 = Enable data scrambling. 0 = Disable data scrambling. When FX mode is selected, this bit will be forced to 0. RW Set by SCRAM_EN pin 21 1 PCSBP 1 = Bypass PCS. 0 = Enable PC. RW Set by PCSBP pin 21 0 FX_SEL 1 = FX mode selected. 0 = Disable FX mode. RW Set by FX_SEL pin |
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