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DSPIC30F Datasheet(PDF) 83 Page - Microchip Technology

No. de pieza DSPIC30F
Descripción Electrónicos  High-Performance Digital Signal Controllers
PDF  220 Pages
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Fabricante Electrónico  MICROCHIP [Microchip Technology]
Página de inicio  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

DSPIC30F Datasheet(HTML) 83 Page - Microchip Technology

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 2004 Microchip Technology Inc.
Preliminary
DS70116C-page 81
dsPIC30F5011/5013
13.0
OUTPUT COMPARE MODULE
This section describes the output compare module and
associated Operational modes. The features provided
by this module are useful in applications requiring
Operational modes, such as:
• Generation of Variable Width Output Pulses
• Power Factor Correction
Figure 13-1 depicts a block diagram of the output
compare module.
The key operational features of the output compare
module include:
• Timer2 and Timer3 Selection mode
• Simple Output Compare Match mode
• Dual Output Compare Match mode
• Simple PWM mode
• Output Compare During Sleep and Idle modes
• Interrupt on Output Compare/PWM Event
These Operating modes are determined by setting the
appropriate bits in the 16-bit OCxCON SFR (where
x = 1,2,3,...,N). The dsPIC devices contain up to 8
compare channels (i.e., the maximum value of N is 8).
OCxRS and OCxR in Figure 13-1 represent the Dual
Compare registers. In the Dual Compare mode, the
OCxR register is used for the first compare and OCxRS
is used for the second compare.
FIGURE 13-1:
OUTPUT COMPARE MODE BLOCK DIAGRAM
OCxR
Comparator
Output
Logic
Q
S
R
OCM<2:0>
Output
OCx
Set Flag bit
OCxIF
OCxRS
Mode Select
3
Note:
Where ‘x’ is shown, reference is made to the registers associated with the respective output compare
channels 1 through N.
OCFA
OCTSEL
01
T2P2_MATCH
TMR2<15:0
TMR3<15:0>
T3P3_MATCH
From GP
(for x = 1, 2, 3 or 4)
or OCFB
(for x = 5, 6, 7 or 8)
01
Timer Module
Enable



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