FN3043 Rev 2.00

Page 2 of 17

Aug 2000

HS-82C54RH

Pinouts

24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE

(SBDIP) MIL-STD-1835 CDIP2-T24

TOP VIEW

24 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

(FLATPACK) MIL-STD-1835 CDFP4-F24

TOP VIEW

1

2

3

4

5

6

7

8

9

10

11

12

D7

D6

D5

D4

D3

D2

D1

D0

CLK 0

OUT 0

GATE 0

GND

16

17

18

19

20

21

22

23

24

15

14

13

VDD

RD

CS

A1

A0

OUT 2

CLK 1

GATE 1

OUT 1

WR

CLK 2

GATE 2

24

23

22

21

20

19

18

17

16

15

14

13

2

3

4

5

6

7

8

9

10

11

12

1

GND

D7

D6

D5

D4

D3

D2

D1

D0

CLK 0

OUT 0

GATE 0

VDD

OUT1

GATE 1

CLK 1

GATE 2

OUT 2

WR

RD

CS

A1

CLK 2

A0

Pin Descriptions

SYMBOL

PIN

NUMBER

TYPE

DESCRIPTION

D7-D0

1-8

I/O

DATA: Bi-directional three state data bus lines, connected to system data bus.

CLK 0

9

I

CLOCK 0: Clock input of Counter 0.

OUT 0

10

O

OUT 0: Output of Counter 0.

GATE 0

11

I

GATE 0: Gate input of Counter 0.

GND

12

GROUND: Power supply connection.

OUT 1

13

O

OUT 1: Output of Counter 1.

GATE 1

14

I

GATE 1: Gate input of Counter 1.

CLK 1

15

I

CLOCK 1: Clock input of Counter 1.

GATE 2

16

I

GATE 2: Gate input of Counter 2.

OUT 2

17

O

OUT 2: Output of Counter 2.

CLK 2

18

I

CLOCK 2: Clock input of Counter 2.

A0, A1

19-20

I

ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write

operations. Normally connected to the system address bus.

A1

A0

Selects

0

0

Counter 0

0

1

Counter 1

1

0

Counter 2

1

1

Control Word Register

CS

21

I

CHIP SELECT: A low on this input enables the HS-82C54RH to respond to RD and WR signals. RD

and WR are ignored otherwise.

RD

22

I

READ: This input is low during CPU read operations.

WR

23

I

WRITE: This input is low during CPU write operations.

VDD

24

VDD: The +5V power supply pin. A 0.1

F capacitor between pins 12 and 24 is recommended for

decoupling.