4LS datasheet(63/115 Pages) AMSCO

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4LS

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

114

│ 62

Address: 0x02

Default Value: 0x00

Access: Read/Write

Bit

Bit Name

Default

Bit Description

3:3

Output Mode

Sets the output transmission mode.

When set to '1' the transmission is

performed at 8-bit (maximum MCLK =

80 MHz).

When set to '0' the transmission is

performed at 12-bit (maximum MCLK =

60 MHz).

2:0

PLL Division

000b

These 3 bits are responsible for the PLL

clock division configuration.

Figure 93:

Frequency Range Programmed by PLL Division

Bit 2

Bit 1

Bit 0

Division

Value

Frequency Range of MCLK

[MHz] for 12-Bit Mode

Frequency Range of MCLK

[MHz] for 8-Bit Mode

37.5

– 60

– 80

– 37.5

– 75

–19

– 38

4.5

– 9

– 18

– 4.5

– 9

9.1.4

Status 3 Register (Address 0x03)

Figure 94:

STS3Reg

Address: 0x03

Default Value: 0x00

Access: Read/Write

Bit

Bit Name

Default

Bit Description

7:7

VBL Top Bottom

Connection

When set to ‘1’ connects the black level

voltage between Top and Bottom

elements.

6:6

VREF Top Bottom

Connection

When set to

‘1’ connects the CDS

reference voltage between Top and

Bottom elements.

5:5

RAMP L1 L2

Connection

When set to ‘1’ connects Ramp Line 1 to

Ramp Line 2 from each segment

individually.

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