4LS datasheet(72/115 Pages) AMSCO

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4LS

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

114

│ 71

9.1.17

Training Sequence 2 Line 1 Register (Address 0x10)

Figure 115:

TSQ2L1Reg

Address: 0x10

Default Value: 0xFF

Access: Read/Write

Bit

Bit Name

Default

Bit Description

7:0

Training

sequence 2

11111111b

Defines the 8 MSBs for word B training

sequence sent over the LVDS driver of Line

1 for FPGA synchronization purposes.

9.1.18

Training Sequence 3 Line 1 Register (Address 0x11)

Figure 116:

TSQ3L1Reg

Address: 0x11

Default Value: 0xA9

Access: Read/Write

Bit

Bit Name

Default

Bit Description

7:0

Training

sequence 3

10101001b

Defines the LSBs for word A and B training

sequence sent over the LVDS driver of Line

1 for FPGA synchronization purposes.

9.1.19

Test Data Serializer Line 1 Register (Address 0x12)

Figure 117:

TDSL1Reg

Address: 0x12

Default Value: 0x40

Access: Read/Write

Bit

Bit Name

Default

Bit Description

7:0

Training test data

01000000b

When the sensor is in training mode,

defines the data pattern to test the

serialization / LVDS data output blocks for

Line 1.

The register value is concatenated with

0x0A (LSB), getting a 12-bit word.

For 12-bit mode, test data is the full 12-bit

word.

For 8-bit mode, the 2 MSB and 2 LSB are

discarded to get a 8-bit test data word.

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