AD9942

Rev. A | Page 19 of 36

CHANNEL A AND CHANNEL B PRECISION TIMING

HIGH SPEED TIMING GENERATION

The AD9942 generates flexible, high speed timing signals using

the Precision Timing core for both channels. This core is the

foundation for generating the timing used for both the CCD

and the AFE, the reset gate RG_X, the horizontal drivers H1X

to H4X, and the SHP/SHD sample clocks. A unique architecture

makes it routine for the system designer to optimize image

quality by providing precise control over the horizontal CCD

readout and the AFE correlated double sampling.

TIMING RESOLUTION

The Precision Timing core uses a 1× master clock input (CLI) as

a reference. This clock should be the same as the CCD pixel

clock frequency. Figure 16 illustrates how the internal timing

core divides the master clock period into 48 steps or edge

positions. Therefore, the edge resolution of the Precision Timing

see the Applications Information section.

HIGH SPEED CLOCK PROGRAMMABILITY

Figure 17 shows how the high speed clocks, RG_X, H1X to

H4X, SHP, and SHD, are generated. The RG_X pulse has

programmable rising and falling edges and can be inverted

using the polarity control. The horizontal clock, H1, has

programmable rising and falling edges and polarity control.

The H2 clock is always the inverse of the H1 clock. Table 17 sum-

marizes the high speed timing registers and their parameters.

Each edge location setting is six bits wide, but only 48 valid edge

locations are available. Therefore, the register values are

mapped into four quadrants, with each quadrant containing

12 edge locations. Table 18 shows the correct register values for

the corresponding edge locations.

NOTES

1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.

2. THERE IS A FIXED DELAY FROM THE CLI_X INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (

P[0]

P[48] = P[0]

P[12]

P[24]

P[36]

1 PIXEL

PERIOD

...

...

CLI_X

POSITION

Figure 16. High Speed Clock Resolution from CLI

H1X/H3X

H2X/H4X

CCD SIGNAL

RG_X

12

3

4

56

PROGRAMMABLE CLOCK POSITIONS:

Figure 17. High Speed Clock Programmable Locations