23

5387B–HIREL–07/05

PC7447A [Preliminary]

Notes:

1. OV

Because these settings may change in future products, it is recommended BVSEL be configured using resistor options,

jumpers, or some other flexible means, with the capability to reconfigure the termination of this signal in the future if neces-

2. Unused address pins must be pulled down to GND and corresponding address parity pins pulled up to OV

3. These pins require weak pull-up resistors (for example, 4.7 K

Ω) to maintain the control signals in the negated state after they

have been actively negated and released by the PC7447A and other bus masters.

4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going

high.

5. This signal must be negated during reset, by pull-up resistor to OV

ensure proper operation.

6. Internal pull up on die.

7. Ignored in 60x bus mode.

8. These signals must be pulled down to GND if unused, or if the PC7447A is in 60x bus mode.

9. These input signals are for factory use only and must be pulled down to GND for normal machine operation.

10. This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect performance.

11. These signals are for factory use only and must be left unconnected for normal machine operation. Some pins that were

NCs on the PC7447, have now been defined for other purposes.

12. These input signals are for factory use only and must be pulled up to OV

13. This pin can externally cause a performance monitor event. Counting of the event is enabled through software.

14. This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation.

15. These pins were NCs on the PC7447. They may be left unconnected for backward compatibility with these devices, but it is

16. These pins were OV

nal device to detect the I/O voltage level present inside the device package. If unused, they must be connected directly to

17. These pins provide connectivity to the on-chip temperature diode that can be used to determine the die junction temperature

of the processor. These pins may be left unterminated if unused.

level present inside the device package. If unused, they must be connected directly to V

19. These pins are internally connected to GND and are intended to allow an external device to detect the processor ground

voltage level present inside the device package. If unused, they must be connected directly to GND or left unconnected.

Note:

Caution must be exercised when performing boundary scan test operations on a board designed for a PC7447A but populated

with an PC7447.

A12, B6, B10, E10

–

Input

BVSEL

D10

–

Input

BVSEL

F1

High

Input

BVSEL

A5

Low

Input

BVSEL

L4

Low

I/O

BVSEL

TSIZ[0:2]

G6, F7, E7

High

Output

BVSEL

TT[0:4]

E5, E6, F6, E9, C5

High

I/O

BVSEL

D3

Low

Output

BVSEL

H8, H10, H12, J7, J9, J11, J13, K8, K10, K12, K14, L7, L9, L11, L13,

M8, M10, M12

––

N/A

V

DD

(15)

A13, A16, A18, B17, B19, C13, E13, E16, F12, F17, F19, G11, G16,

H14, H17, H19, M14, M16, M18, N15, N17, P16, P18

––

N/A

V

(18)

G13, N12

–

–

N/A

Table 8-1.

Pinout Listing for the PC7447A, 360 HITCE Package (Continued)

Signal Name

Pin Number

Active

I/O