36

5387B–HIREL–07/05

PC7447A [Preliminary]

Notes:

1. PLL_CFG[0:4] settings not listed are reserved.

2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO

3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled. However, the

bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must be driven at one-half the

clocked at SYSCLK frequency. This mode is intended for factory use and emulator tool use only.

Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.

4. In PLL-off mode, no clocking occurs inside the PC7447A regardless of the SYSCLK input.

01011

13x

2x

650

(1300)

865

(1730)

975

(1950)

1079

(2158)

1300

(2600)

11100

13.5x

2x

675

(1350)

900

(1800)

1013

(2026)

1121

(2242)

1350

(2700)

11001

14x

2x

700

(1400)

933

(1866)

1050

(2100)

1162

(2324)

1400

(2800)

00011

15x

2x

750

(1500)

1000

(2000)

1125

(2250)

1245

(2490)

11011

16x

2x

800

(1600)

1066

(2132)

1200

(2400)

1328

(2656)

00001

17x

2x

850

(1900)

1132

(2264)

1275

(2550)

1411

(2822)

00101

18x

2x

600

(1200)

900

(1800)

1200

(2400)

1350

(2700)

00111

20x

2x

667

(1334)

1000

(2000)

1332

(2664)

01001

21x

2x

700

(1400)

1050

(2100)

1399

(2797)

01101

24x

2x

800

(1600)

1200

(2400)

11101

28x

2x

933

(1866)

1400

(2800)

00110

PLL bypass

PLL off, SYSCLK clocks core circuitry directly

11110

PLL off

PLL off, no core clocking occurs

Table 13-1.

PC7447A Microprocessor PLL Configuration Example for 1420-MHz Parts (Continued)